Silicon carbide trench MOSFET having reduced on-resistance, increased dielectric withstand voltage, and reduced threshold voltage

Patent metadata

Field	Value
Publication number	US-9024329-B2
Application number	US-201314049810-A
Country	US
Kind code	B2
Filing date	Oct 9, 2013
Priority date	May 20, 2008
Publication date	May 5, 2015
Grant date	May 5, 2015

Abstract

A semiconductor device (A1) includes a first n-type semiconductor layer (11), a second n-type semiconductor layer (12), a p-type semiconductor layer (13), a trench (3), an insulating layer (5), a gate electrode (41), and an n-type semiconductor region (14). The p-type semiconductor layer (13) includes a channel region that is along the trench (3) and in contact with the second n-type semiconductor layer (12) and the n-type semiconductor region (14). The size of the channel region in the depth direction x is 0.1 to 0.5 μm. The channel region includes a high-concentration region where the peak impurity concentration is approximately 1×1018 cm−3. The semiconductor device A1 thus configured allows achieving desirable values of on-resistance, dielectric withstand voltage and threshold voltage.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a first semiconductor layer having a first conductivity type and made of silicon carbide;
a second semiconductor layer made of silicon carbide, provided on the first semiconductor layer and having a second conductivity type opposite to the first conductivity type;
a trench penetrating through the second semiconductor layer to reach the first semiconductor layer;
an insulating layer formed at a bottom and a side…

Assignees

• Rohm Co Ltd

Inventors

• Nakano Yuki

Classifications

• H10D30/0297

  Electricity · mapped topic

• H10D12/038

  Electricity · mapped topic

• H10D62/111

  Electricity · mapped topic

• H10D64/516

  Electricity · mapped topic

• H10D64/62

  Electricity · mapped topic