Metallization structure for high power microelectronic devices

US9024327B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9024327-B2
Application numberUS-95636607-A
CountryUS
Kind codeB2
Filing dateDec 14, 2007
Priority dateDec 14, 2007
Publication dateMay 5, 2015
Grant dateMay 5, 2015

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  2. Abstract

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Abstract

Official abstract text for this publication.

A semiconductor device structure is disclosed that includes a wide-bandgap semiconductor portion selected from the group consisting of silicon carbide and the Group III nitrides. An interconnect structure is made to the semiconductor portion, and the interconnect structure includes at least two diffusion barrier layers alternating with two respective high electrical conductivity layers. The diffusion barrier layers have a coefficient of thermal expansion different from and lower than the coefficient of thermal expansion of the high electrical conductivity layers. The difference in the respective coefficients of thermal expansions are large enough to constrain the expansion of the high conductivity layers but less than a difference that would create a strain between adjacent layers that would exceed the bond strength between the layers.

First claim

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The invention claimed is: 1. A semiconductor device structure comprising: a wide-bandgap semiconductor portion selected from the group consisting of silicon carbide and Group III nitrides; an interconnect structure to said wide-bandgap semiconductor portion, said interconnect structure comprising a plurality of diffusion barrier layers alternating with a plurality of high electrical conductivity layers, the plurality of diffusion barrier layers and the plurality of high electric…

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What does patent US9024327B2 cover?
A semiconductor device structure is disclosed that includes a wide-bandgap semiconductor portion selected from the group consisting of silicon carbide and the Group III nitrides. An interconnect structure is made to the semiconductor portion, and the interconnect structure includes at least two diffusion barrier layers alternating with two respective high electrical conductivity layers. The dif…
Who is the assignee on this patent?
Ward Allan, Henning Jason, Cree Inc
What technology area does this patent fall under?
Primary CPC classification H10D62/8325. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 05 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).