Semiconductor device and method for forming the same
US-2024395669-A1 · Nov 28, 2024 · US
Method and design of an RF thru-via interconnect
US9024326B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9024326-B2 |
| Application number | US-201213879696-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 18, 2012 |
| Priority date | Jul 18, 2011 |
| Publication date | May 5, 2015 |
| Grant date | May 5, 2015 |
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Abstract
Official abstract text for this publication.
In summary, a vertical metalized transition in the form of a via goes from the back side of a high thermal conductivity substrate and through any semiconductor layers thereon to a patterned metalized strip, with the substrate having a patterned metalized layer on the back side that is provided with a keep away zone dimensioned to provide impedance matching for RF energy coupled through the substrate to the semiconductor device while at the same time permitting the heat generated by the semiconductor device to flow through the high thermal conductivity substrate, through the back side of the substrate and to a beat sink.
First claim
Opening claim text (preview).
What is claimed is: 1. In a method of forming a semiconductor RF connection for improved thermal management on a semiconductor chip, wherein the improvement comprises: forming a vertical transition passing through the semiconductor chip; connecting RF signals through the back of the semiconductor chip at the vertical transition, enabling backside heat sinking, wherein the back of the chip comprises a patterned metalized layer having a keep away surrounding the base of the vertic…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10W20/20Primary
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9024326B2 cover?
- In summary, a vertical metalized transition in the form of a via goes from the back side of a high thermal conductivity substrate and through any semiconductor layers thereon to a patterned metalized strip, with the substrate having a patterned metalized layer on the back side that is provided with a keep away zone dimensioned to provide impedance matching for RF energy coupled through the subs…
- Who is the assignee on this patent?
- Actis Robert, Chao Pane-Chane, Lender Jr Robert J, and 4 more
- What technology area does this patent fall under?
- Primary CPC classification H10W20/20. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue May 05 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).