Semiconductor device
US-2024421048-A1 · Dec 19, 2024 · US
Wiring structure and display device
US9024322B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9024322-B2 |
| Application number | US-201214116935-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 12, 2012 |
| Priority date | May 13, 2011 |
| Publication date | May 5, 2015 |
| Grant date | May 5, 2015 |
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Abstract
Official abstract text for this publication.
Provided is a technique that allows oxidation of Cu wires to be effectively prevented during plasma processing when forming a passivation film for a display device that utilizes an oxide semiconductor layer. This wiring structure comprises a semiconductor layer (oxide semiconductor) for a thin film transistor, a Cu alloy film (laminated structure comprising a first layer (X) and a second layer (Z)), and a passivation film that are formed on a substrate, starting from the substrate side. The first layer (X) is made of an element that exhibits low electrical resistivity, such as pure Cu; and the second layer contains a plasma-oxidation-resistance improving element. The second layer (Z) is directly connected, at least partially, to the passivation film.
First claim
Opening claim text (preview).
The invention claimed is: 1. A Cu alloy film, for a wiring structure comprising: an oxide semiconductor layer of a thin-film transistor; the Cu alloy film, which is an electrode; and a passivation film, wherein the oxide semiconductor layer, the Cu alloy film, and the passivation film are arranged above a substrate in that order from the substrate, the Cu alloy film has a multilayer structure including a first layer (X) and second layer (Z) arranged in that order from the substrat…
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Classifications
- H10W72/00Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9024322B2 cover?
- Provided is a technique that allows oxidation of Cu wires to be effectively prevented during plasma processing when forming a passivation film for a display device that utilizes an oxide semiconductor layer. This wiring structure comprises a semiconductor layer (oxide semiconductor) for a thin film transistor, a Cu alloy film (laminated structure comprising a first layer (X) and a second layer …
- Who is the assignee on this patent?
- Miki Aya, Kugimiya Toshihiro, Kobe Steel Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10W72/00. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue May 05 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).