Hardware countermeasures in a fault tolerant security architecture
US-2024370591-A1 · Nov 7, 2024 · US
US9020148B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9020148-B2 |
| Application number | US-201113030317-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 18, 2011 |
| Priority date | Feb 19, 2010 |
| Publication date | Apr 28, 2015 |
| Grant date | Apr 28, 2015 |
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Official abstract text for this publication.
A method for protecting a key intended to be used by an electronic circuit in an encryption or decryption algorithm, including the steps of: submitting the key to a first function taking a selection value into account; storing all or part of the result of this function in at least two registers; when the key is called by the algorithm, reading the contents of said registers and submitting them to a second function taking into account all or part of the bits of the registers; and providing the result of the combination as an input for the algorithm, the second function being such that the provided result corresponds to the key.
Opening claim text (preview).
What is claimed is: 1. A method for protecting a key to be used by an electronic circuit in an algorithm, comprising acts of: submitting the key to a first function taking a selection value into account; storing at least one portion of a first result of applying the first function to the key in at least two registers each having a same size as the key, wherein the at least one portion of the first result comprises more bits than the key; when the algorithm issues a call for th…
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