Page buffer performing memory operation
US-2024274171-A1 · Aug 15, 2024 · US
US9019784B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9019784-B2 |
| Application number | US-201314100684-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 9, 2013 |
| Priority date | Sep 10, 2013 |
| Publication date | Apr 28, 2015 |
| Grant date | Apr 28, 2015 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A data training device includes a training control block configured to activate driving signals for driving a bit line sense amplifier, with a word line deactivated, when a write training operation is performed according to a mode register write command; and the bit line sense amplifier configured to store training data according to the driving signals from the training control block.
Opening claim text (preview).
What is claimed is: 1. A data training device comprising: a training control block configured to activate driving signals for driving a bit line sense amplifier, with a word line deactivated, when a write training operation is performed according to a mode register write command; the bit line sense amplifier configured to store training data according to the driving signals from the training control block; and a cell array configured to allow data already stored therein to be…
Related publications grouped by family.
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Answers are generated from the same data shown on this page.