Memory device and in-memory search method thereof
US-2024274164-A1 · Aug 15, 2024 · US
Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules
US9019779B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9019779-B2 |
| Application number | US-201314046756-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 4, 2013 |
| Priority date | May 8, 2003 |
| Publication date | Apr 28, 2015 |
| Grant date | Apr 28, 2015 |
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Abstract
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A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time. In an alternate embodiment, the printed circuit board includes a driver sector electrically isolated from the other sectors and having a multi-layer structure, the driver being attached to the driver sector.
First claim
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What is claimed: 1. An apparatus comprising: a plurality of memory devices; a printed circuit board having a plurality of sectors, each sector of the plurality of sectors being electrically isolated from other sectors of the plurality of sectors, wherein each sector of the plurality of sectors has a respective at least one of the plurality of memory devices attached thereto; and a plurality of drivers attached to the printed circuit board, wherein each driver of the plurality…
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- What does patent US9019779B2 cover?
- A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A d…
- Who is the assignee on this patent?
- Micron Technology Inc
- What technology area does this patent fall under?
- Primary CPC classification G11C5/02. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Apr 28 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).