Neural network computation circuit, control circuit therefor, and control method therefor
US-2024411520-A1 · Dec 12, 2024 · US
US9019746B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9019746-B2 |
| Application number | US-201313844923-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 16, 2013 |
| Priority date | Nov 14, 2012 |
| Publication date | Apr 28, 2015 |
| Grant date | Apr 28, 2015 |
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A resistive memory device includes a plurality of memory cells, each of which is configured to store a normal data, a first reference data corresponding to a first resistance state and a second reference data corresponding to a second resistance state, a data copy unit configured to temporarily store the normal data read from a selected memory cell and generate a copied cell current based on the stored normal data, a mirroring block configured to temporarily store the first and second reference data read from the selected memory cell, and to generate a first reference current and a second reference current based on the stored first and second reference data, respectively, and a sensing unit configured to sense the stored normal data based on the copied cell current and the first reference current and the second reference current.
Opening claim text (preview).
What is claimed is: 1. A resistive memory device, comprising: a plurality of memory cells, each of which is configured to store a normal data, a first reference data corresponding to a first resistance state and a second reference data corresponding to a second resistance state; a data copy unit configured to temporarily store the normal data read from a selected memory cell and generate a copied cell current based on the stored normal data; a mirroring block configured to tem…
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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