Elimination of minimal use threads via quad merging
US-2015379764-A1 · Dec 31, 2015 · US
Z-culling method, three-dimensional graphics processing method and apparatus threrof
US9019271B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9019271-B2 |
| Application number | US-201213480477-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 25, 2012 |
| Priority date | May 25, 2011 |
| Publication date | Apr 28, 2015 |
| Grant date | Apr 28, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A Z culling method, a three-dimensional graphics processing method using Z-culling, and an apparatus thereof are provided. The Z-culling method includes the following steps. A Z cache memory is provided to buffer a cover mask and a dynamic maximum depth value corresponding to each tile. A draw mask, a draw maximum depth value, and a draw minimum depth value calculated according to the tile and a drawn part are obtained. Moreover, whether the drawn part is completely included in a known part of the cover mask is judged, and coordinated with a comparison of the draw minimum depth value and the dynamic maximum depth value, so as to determine whether to discard the drawn part and whether to update the cover mask and the dynamic maximum depth value in the Z cache memory. Accordingly, the bandwidth taken up in the system memory is reduced efficiently.
First claim
Opening claim text (preview).
What is claimed is: 1. A Z-culling method adapted for a three-dimensional (3D) graphics processing apparatus, the Z-culling method comprising: providing a Z cache memory to buffer a cover mask and a dynamic maximum depth value corresponding to one of a plurality of tiles of a rasterized screen, wherein the cover mask represents a pixel location of a known part in said one of the plurality of tiles, and the dynamic maximum depth value is the maximum depth value of all pixels in the…
Assignees
Inventors
Classifications
Physics · mapped topic
- G06T15/405Primary
Physics · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9019271B2 cover?
- A Z culling method, a three-dimensional graphics processing method using Z-culling, and an apparatus thereof are provided. The Z-culling method includes the following steps. A Z cache memory is provided to buffer a cover mask and a dynamic maximum depth value corresponding to each tile. A draw mask, a draw maximum depth value, and a draw minimum depth value calculated according to the tile and …
- Who is the assignee on this patent?
- Liang ai-min, Via Tech Inc
- What technology area does this patent fall under?
- Primary CPC classification G06T15/405. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Apr 28 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).