Mixed-radix and/or mixed-mode switch matrix architecture and integrated circuit, and method of operating same
US-9503092-B2 · Nov 22, 2016 · US
Dual-port positive level sensitive reset preset data retention latch
US9018976B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9018976-B2 |
| Application number | US-201314080183-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 14, 2013 |
| Priority date | Aug 26, 2013 |
| Publication date | Apr 28, 2015 |
| Grant date | Apr 28, 2015 |
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Abstract
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In an embodiment of the invention, a dual-port positive level sensitive reset preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low, rest control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D 2 , the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D 2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.
First claim
Opening claim text (preview).
What is claimed is: 1. A dual-port positive level sensitive reset preset data retention latch comprising: a clocked inverter configured to receive a first data bit (D 1 ), clock signal (CKT), a binary logical compliment clock signal (CLKZ), a preset control signal (PRE), a reset control signal (REN) and a binary logical compliment retention mode control signal (RETN) wherein the signals CKT, CLKZ, REN, RETN, and PRE determine whether a data output (QN) from the clocked inverter is…
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- H03K19/1735Primary
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9018976B2 cover?
- In an embodiment of the invention, a dual-port positive level sensitive reset preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low, rest control signal REN is high and retention control signal RET is low. The dual-port latch is configured to rec…
- Who is the assignee on this patent?
- Texas Instruments Inc
- What technology area does this patent fall under?
- Primary CPC classification H03K19/1735. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 28 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).