Method and system to verify the reliability of electronic devices

Patent metadata

Field	Value
Publication number	US-9018965-B2
Application number	US-200913142528-A
Country	US
Kind code	B2
Filing date	Nov 26, 2009
Priority date	Dec 29, 2008
Publication date	Apr 28, 2015
Grant date	Apr 28, 2015

Abstract

To verify robustness with respect to electrical overstresses of an electronic circuit under test, the latter is exposed to electrical overstresses, and the behavior thereof is monitored. In particular, both the testing of the electronic circuit in dynamic conditions is performed by causing it to be traversed by the currents that characterize operation thereof, and by exposing at least one supply line of the electronic circuit under test to electrical overstresses and the testing of the electronic circuit under test in static conditions, without causing it to be traversed by the currents that characterize operation thereof, and by exposing to electrical overstresses both the supply and the input and/or output lines of the electronic circuit under test. The device for generating the overstresses can be mounted on a circuit board, which can be coupled as daughter board to a mother board, on which the electronic circuit under test is mounted.

First claim

That which is claimed is:

1. A method of testing an electronic circuit comprising:
operating the electronic circuit while exposing the electronic circuit to electrical overstresses;
generating the electrical overstresses as an electrical pulse train, with amplitudes, durations, pulse widths, pulse train frequency, and overshoot voltages of the electrical pulse train being settable in real time;
simultaneously superimposing the electrical overstresses on a plurality of differen…

Assignees

• Ricci Raffaele
• St Microelectronics Srl

Inventors

• Ricci Raffaele

Classifications

• G01R31/2849

  Physics · mapped topic

• G01R31/002 Primary

  Physics · mapped topic