All-tungsten scheme for source/drain contact, source/drain via, and gate via
US-2024395618-A1 · Nov 28, 2024 · US
Semiconductor device having barrier metal layer
US9018764B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9018764-B2 |
| Application number | US-201314018637-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 5, 2013 |
| Priority date | Sep 10, 2012 |
| Publication date | Apr 28, 2015 |
| Grant date | Apr 28, 2015 |
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Abstract
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According to one embodiment, a semiconductor device having an interlayer insulating film, a molybdenum containing layer, a barrier metal layer and a plug material layer is provided. The interlayer insulating film is formed on a substrate or on a conductive layer formed on a substrate. The interlayer insulating film has a hole reaching the substrate or the conductive layer. The molybdenum containing layer is formed in the substrate or in the conductive layer at a bottom portion of the hole. The barrier metal layer is formed on the molybdenum containing layer and on a side surface of the hole. A portion of the barrier metal layer is formed on the side surface contains at least molybdenum. A portion of the barrier metal layer is formed on the molybdenum containing layer includes at least a molybdenum silicate nitride film. The plug material layer is formed via the barrier metal layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device comprising: a substrate; and a laminated body formed on the substrate and serves as an interconnection or an electrode, wherein the laminated body includes a semiconductor layer containing silicon which is formed as a first wiring material or an electrode material above the substrate, a barrier metal layer which is formed on the semiconductor layer and contains molybdenum, and a metal layer which is formed on the barrier metal…
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Electricity · mapped topic
Electricity · mapped topic
- H10W20/425Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9018764B2 cover?
- According to one embodiment, a semiconductor device having an interlayer insulating film, a molybdenum containing layer, a barrier metal layer and a plug material layer is provided. The interlayer insulating film is formed on a substrate or on a conductive layer formed on a substrate. The interlayer insulating film has a hole reaching the substrate or the conductive layer. The molybdenum contai…
- Who is the assignee on this patent?
- Toshiba Kk
- What technology area does this patent fall under?
- Primary CPC classification H10W20/425. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 28 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).