Semiconductor device
US-2024290673-A1 · Aug 29, 2024 · US
Method for manufacturing semiconductor device, and semiconductor device
US9018745B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9018745-B2 |
| Application number | US-201313898410-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 20, 2013 |
| Priority date | Jun 27, 2012 |
| Publication date | Apr 28, 2015 |
| Grant date | Apr 28, 2015 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
A method according to the invention has a bonding process of mounting a semiconductor chip on an upper surface of a die pad that has the upper surface whose area is larger than a reverse side of the semiconductor chip. It also has a sealed body formation process of sealing the semiconductor chip so that an undersurface opposite to the upper surface of the die pad may be exposed after the bonding process. Here, the upper surface of the die pad is arranged around an area over which the semiconductor chip is mounted, and has a hollow part arrangement area in which a groove or multiple holes are formed. Moreover, surface roughness of the upper surface is made coarser than surface roughness of the undersurface.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device, comprising: a die pad that has a first plane and a second plane located on the opposite side of the first plane; a plurality of leads arranged next to the die pad; a semiconductor chip that has a surface, a plurality of electrodes formed over the surface, and a reverse side located on the opposite side of the surface, and is mounted over a chip mounting area of the first plane of the die pad; a plurality of first wires that elec…
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Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9018745B2 cover?
- A method according to the invention has a bonding process of mounting a semiconductor chip on an upper surface of a die pad that has the upper surface whose area is larger than a reverse side of the semiconductor chip. It also has a sealed body formation process of sealing the semiconductor chip so that an undersurface opposite to the upper surface of the die pad may be exposed after the bondin…
- Who is the assignee on this patent?
- Renesas Electronics Corp, Renesas Corp
- What technology area does this patent fall under?
- Primary CPC classification H10W74/127. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 28 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).