Gate isolation features and methods of fabricating the same in semiconductor devices
US-2024379673-A1 · Nov 14, 2024 · US
Semiconductor device and method for fabricating the same
US9018708B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9018708-B2 |
| Application number | US-201213717595-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 17, 2012 |
| Priority date | Aug 31, 2012 |
| Publication date | Apr 28, 2015 |
| Grant date | Apr 28, 2015 |
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Abstract
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A semiconductor device includes a substrate including a cell region and a peripheral circuit region, buried gates formed in the substrate of the cell region, a bit line formed over the cell region between the buried gates and including a first barrier layer, and a gate formed over the peripheral circuit region and including a second barrier layer and a third barrier layer.
First claim
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What is claimed is: 1. A semiconductor device comprising: a substrate including a cell region and a peripheral circuit region; buried gates formed in the substrate of the cell region; a bit line formed over the cell region between the buried gates and including a first barrier layer; and a gate formed over the peripheral circuit region and including a second barrier layer and a third barrier layer, wherein the second barrier layer has a thickness greater than that of the f…
Assignees
Inventors
Classifications
- H10D84/83Primary
Electricity · mapped topic
- H01L27/088Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9018708B2 cover?
- A semiconductor device includes a substrate including a cell region and a peripheral circuit region, buried gates formed in the substrate of the cell region, a bit line formed over the cell region between the buried gates and including a first barrier layer, and a gate formed over the peripheral circuit region and including a second barrier layer and a third barrier layer.
- Who is the assignee on this patent?
- Sk Hynix Inc
- What technology area does this patent fall under?
- Primary CPC classification H10D84/83. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 28 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).