Cell placement optimization
US-2024371942-A1 · Nov 7, 2024 · US
Non-planar semiconductor device having active region with multi-dielectric gate stack
US9018680B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9018680-B2 |
| Application number | US-201414340981-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 25, 2014 |
| Priority date | Sep 27, 2012 |
| Publication date | Apr 28, 2015 |
| Grant date | Apr 28, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device, comprising: a semiconductor substrate comprising a first semiconductor material; a second layer above the semiconductor substrate, the second layer comprising a second material different from the first semiconductor material; a nanowire above the second layer, the nanowire comprising a third material different than the second material, the nanowire having a channel region; a source region to a first side of the channel region an…
Assignees
Inventors
Classifications
Electricity · mapped topic
- H10D30/60Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9018680B2 cover?
- Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group …
- Who is the assignee on this patent?
- Dewey Gilbert, Radosavljevic Marko, Pillarisetty Ravi, and 3 more
- What technology area does this patent fall under?
- Primary CPC classification H10D30/60. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 28 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).