Semiconductor device processing with reduced wiring puddle formation

Patent metadata

Field	Value
Publication number	US-9018097-B2
Application number	US-201213648329-A
Country	US
Kind code	B2
Filing date	Oct 10, 2012
Priority date	Oct 10, 2012
Publication date	Apr 28, 2015
Grant date	Apr 28, 2015

Abstract

A method of forming an interconnect structure for a semiconductor device includes forming a lower antireflective coating layer over a dielectric layer; forming an organic planarizing layer on the lower antireflective coating layer; transferring a wiring pattern through the organic planarizing layer; transferring the wiring pattern through the lower antireflective coating layer; and transferring the wiring pattern through the dielectric layer, wherein unpatterned portions of the lower antireflective coating layer serve as an etch stop layer so as to prevent any bubble defects present in the organic planarizing layer from being transferred to the dielectric layer.

First claim

The invention claimed is:

1. A method of forming an interconnect structure for a semiconductor device, the method comprising:
forming a lower antireflective coating layer over a dielectric layer;
forming an organic planarizing layer on the lower antireflective coating layer;
transferring a wiring pattern through the organic planarizing layer;
forming an upper antireflective coating layer over the organic planarizing layer;
transferring the wiring pattern through the lower…

Assignees

• IBM

Inventors

• Dyer Thomas W
• Henry Hanako
• Ko Tze-Man
• Xu Yiheng
• Yao Shaoning

Classifications

• H10P76/2043

  Electricity · mapped topic

• H10P50/287

  Electricity · mapped topic

• H10P50/283

  Electricity · mapped topic

• H10P50/73

  Electricity · mapped topic

• H10W20/081 Primary

  Electricity · mapped topic