Method of fabricating memory device with charge storage layer at gap located side of gate dielectric underneath the gate

Patent metadata

Field	Value
Publication number	US-9018085-B2
Application number	US-201414198320-A
Country	US
Kind code	B2
Filing date	Mar 5, 2014
Priority date	Nov 24, 2011
Publication date	Apr 28, 2015
Grant date	Apr 28, 2015

Abstract

A method for fabricating a memory device of this invention includes at least the following steps. A tunnel dielectric layer is formed over a substrate. A gate is fowled over the tunnel dielectric layer. At least one charge storage layer is formed between the gate and the tunnel dielectric layer. Two doped regions are formed in the substrate beside the gate. A word line is formed on and electrically connected to the gate, wherein the word line having a thickness greater than a thickness of the gate.

First claim

What is claimed is:

1. A method for fabricating a memory device, comprising:
forming a tunnel dielectric layer over a substrate;
forming a first portion of a conductive layer over the tunnel dielectric layer;
forming at least one charge storage layer between the first portion of the conductive layer and the tunnel dielectric layer;
forming two doped regions in the substrate beside the first portion of the conductive layer; and
forming a second portion of the conductive lay…

Assignees

• Macronix Int Co Ltd

Inventors

• Yan Shih-Guei
• Tsai Wen-Jer
• Cheng Cheng-Hsien

Classifications

• H10D64/037

  Electricity · mapped topic

• H10D64/035

  Electricity · mapped topic

• H10D30/6893 Primary

  Electricity · mapped topic

• H10D30/697

  Electricity · mapped topic

• H10D30/681

  Electricity · mapped topic