Semiconductor storage device and method of manufacturing the same

US9018076B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9018076-B2
Application numberUS-201313746304-A
CountryUS
Kind codeB2
Filing dateJan 21, 2013
Priority dateOct 29, 2009
Publication dateApr 28, 2015
Grant dateApr 28, 2015

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  2. Abstract

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  5. First independent claim

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Abstract

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A semiconductor storage device includes: memory cells including a transistor and a capacitor; bit lines; word lines; and sense amplifiers including first and second sense amplifiers, wherein the memory cells includes: a first memory cell group sharing a first auxiliary word line; and a second memory cell group sharing a second auxiliary word line, wherein the word lines includes a first word line coupled to the first auxiliary word line and a second word line coupled to the second auxiliary word line, the first word line is coupled to the first auxiliary word line in a first word line contact region, the second word line is coupled to the second auxiliary word line in a second word line contact region, the bit lines includes first and second bit lines coupled to the first sense amplifier on both sides of the first word line contact region.

First claim

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The invention claimed is: 1. A method of manufacturing a semiconductor storage device, the method comprising: forming element isolation trenches in a semiconductor substrate, the element isolation trenches identifying active regions arranged in a matrix pattern extending in a first direction and a second direction, each of the active regions including a transistor region and a capacitor region; filling the element isolation trenches with an element isolation insulating film; r…

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What does patent US9018076B2 cover?
A semiconductor storage device includes: memory cells including a transistor and a capacitor; bit lines; word lines; and sense amplifiers including first and second sense amplifiers, wherein the memory cells includes: a first memory cell group sharing a first auxiliary word line; and a second memory cell group sharing a second auxiliary word line, wherein the word lines includes a first word li…
Who is the assignee on this patent?
Fujitsu Semiconductor Ltd
What technology area does this patent fall under?
Primary CPC classification H10D64/011. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 28 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).