Metal gates for semiconductor devices and method thereof
US-2024429281-A1 · Dec 26, 2024 · US
Horizontal epitaxy furnace for channel SiGe formation
US9018065B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9018065-B2 |
| Application number | US-201213466234-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 8, 2012 |
| Priority date | May 8, 2012 |
| Publication date | Apr 28, 2015 |
| Grant date | Apr 28, 2015 |
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Abstract
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A method and apparatus are provided for recessing a channel region of the PFET and epitaxially growing channel SiGe in the recessed region inside of a horizontally oriented processing furnace. Embodiments include forming an n-channel region and a p-channel region in a front side of a wafer and at least one additional wafer, the n-channel and p-channel regions corresponding to locations for forming an NFET and a PFET, respectively; placing the wafers inside a horizontally oriented furnace having a top surface and a bottom surface, with the wafers oriented vertically between the top and bottom surfaces; recessing the p-channel regions of the wafers inside the furnace; and epitaxially growing cSiGe without hole defects in the recessed p-channel regions inside the furnace.
First claim
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What is claimed is: 1. A method comprising: forming an n-channel region and a p-channel region in a front side of a wafer, the n-channel and p-channel regions corresponding to locations for forming a negative field-effect transistor (NFET) and a positive field-effect transistor (PFET), respectively; placing the wafer in a wafer holder inside a horizontally oriented furnace having a top surface, a bottom surface, and a gas exhaust, with the wafer oriented vertically between the t…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9018065B2 cover?
- A method and apparatus are provided for recessing a channel region of the PFET and epitaxially growing channel SiGe in the recessed region inside of a horizontally oriented processing furnace. Embodiments include forming an n-channel region and a p-channel region in a front side of a wafer and at least one additional wafer, the n-channel and p-channel regions corresponding to locations for form…
- Who is the assignee on this patent?
- Wasyluk Joanna, Chow Yew Tuck, Kronholz Stephan, and 3 more
- What technology area does this patent fall under?
- Primary CPC classification H10D84/0167. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 28 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).