Memory devices having reduced interference between floating gates and methods of fabricating such devices

Patent metadata

Field	Value
Publication number	US-9018059-B2
Application number	US-201313866698-A
Country	US
Kind code	B2
Filing date	Apr 19, 2013
Priority date	Jun 21, 2006
Publication date	Apr 28, 2015
Grant date	Apr 28, 2015

Abstract

A memory array comprising transistors having isolated inter-gate dielectric regions with respect to one another. Transistors are formed such that each of the transistors in the array has a charge storage region such as a floating gate, a control gate and an inter-gate dielectric layer therebetween. The inter-gate dielectric layer for each transistor is isolated from the inter-gate dielectric of each of the other transistors in the array.

First claim

What is claimed is:

1. A method of fabricating a floating gate memory array comprising:
disposing a gate oxide layer on a substrate;
disposing a floating gate layer on the gate oxide layer;
disposing an inter-gate dielectric layer on the floating gate layer;
etching a plurality of substantially parallel trenches through each of the inter-gate dielectric layer, the floating gate layer, the gate oxide layer and the substrate to form a plurality of isolated stacked regions;
f…

Assignees

• Micron Technology Inc

Inventors

• Aritome Seiichi

Classifications

• H10W10/011

  Electricity · mapped topic

• H10W10/10 Primary

  Electricity · mapped topic

• H01L21/762 Primary

  Electricity · mapped topic

• H01L27/11521

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic