Electronic device and method of manufacturing the same
US-2024404904-A1 · Dec 5, 2024 · US
Microelectronic packages and methods for the fabrication thereof
US9018045B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9018045-B2 |
| Application number | US-201313942540-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 15, 2013 |
| Priority date | Jul 15, 2013 |
| Publication date | Apr 28, 2015 |
| Grant date | Apr 28, 2015 |
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- Title
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Abstract
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Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method comprises encapsulating a first semiconductor die having one or more core redistribution layers formed thereover in an outer molded body. The outer molded body has a portion, which circumscribes the core redistribution layer. One or more topside redistribution layers are produced over the core redistribution layer. A contact array is formed over the topside redistribution layer and electrically coupled to the first semiconductor die encapsulated in the outer molded body through the topside redistribution layers and the core redistribution layers.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for fabricating a microelectronic package, comprising: encapsulating a first semiconductor die having one or more core redistribution layers formed thereover in an outer molded body, the outer molded body having a portion circumscribing the core redistribution layers; producing one or more topside redistribution layers over the core redistribution layers; and forming a contact array over the topside redistribution layers and electrically coupled…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9018045B2 cover?
- Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method comprises encapsulating a first semiconductor die having one or more core redistribution layers formed thereover in an outer molded body. The outer molded body has a portion, which circumscribes the core redistribution layer. One or more topside redistribution layers are pro…
- Who is the assignee on this patent?
- Yap Weng Foong, Mitchell Douglas G, Freescale Semiconductor Inc
- What technology area does this patent fall under?
- Primary CPC classification H10W74/121. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 28 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).