Method for forming interposers and stacked memory devices

Patent metadata

Field	Value
Publication number	US-9016552-B2
Application number	US-201414216517-A
Country	US
Kind code	B2
Filing date	Mar 17, 2014
Priority date	Mar 15, 2013
Publication date	Apr 28, 2015
Grant date	Apr 28, 2015

Abstract

Methods for forming a stacking interposer are provided that create a more compact and/or reliable interposer cavity. According to one method, a segmentation process that partially cuts a multi-cell, multi-layer PCB panel to a controlled depth along the internal walls/edges of a cavity region with each of the interposer cell sites defined within the PCB panel is used. The material within the cavity region is then removed (by routing) to a controlled depth to form the internal cavity for each interposer cell site. Pillars may then be removed from the PCB panel. As a result of the initial partial cuts of the internal walls of the cavity region, the corners of the cavities may have a square configuration for fitting over the top of a BGA/memory device (which has very square corners).

First claim

The invention claimed is:

1. A method of manufacturing a stacking interposer, comprising:
forming a multi-cell, multilayer printed circuit board panel having a plurality of interposer cell sites;
slotting the panel using a diamond saw process to form inner walls of cell cavities;
forming a cavity at each interposer cell site on the panel using the diamond saw process, the inner corners of each cavity having a square configuration;
removing remaining material left behind by s…

Assignees

• Sanmina Corp

Inventors

• Sweere Paul

Classifications

• H10W90/724

  Electricity · mapped topic

• H10W72/07236

  Electricity · mapped topic

• H10W72/07233

  Electricity · mapped topic

• H10W72/01271

  Electricity · mapped topic

• H10W72/01215

  Electricity · mapped topic