Systems and methods for procedure return address verification

Patent metadata

Field	Value
Publication number	US-9015835-B2
Application number	US-201313924591-A
Country	US
Kind code	B2
Filing date	Jun 23, 2013
Priority date	Jun 23, 2013
Publication date	Apr 21, 2015
Grant date	Apr 21, 2015

Abstract

An example processing system may comprise: a stack pointer configured to reference a first return address stored on a stack; a return address buffer pointer configured to reference a second return address stored in a return address buffer; and a return address verification logic configured, responsive to receiving a return instruction, to compare the first return address to the second return address.

First claim

The invention claimed is:

1. A processing system, comprising:
a stack pointer configured to reference a first return address stored on a stack;
a return address buffer pointer configured to reference a second return address stored in a return address buffer; and
a return address verification logic configured to:
responsive to receiving a return instruction, compare the first return address to the second return address, and
responsive to receiving a return address buffer modification instruction, perform at least one of: storing a return address in the return address buffer or removing a return address from the return address buffer, wherein the return address buffer modification instruction is a privileged instruction.

2. The processing system of claim 1 , wherein the return address verification logic is further configured to execute the return instruction responsive to determining that the first return address is equal to the second return address.

3. The processing system of claim 1 , wherein the return address verification logic is further configured to generate a stack fault exception responsive to determining that the first return address differs from the second return address.

4. The processing system of claim 1 , wherein the return address verification logic is further configured, responsive to receiving a call instruction, to store a return address on the stack and in the return address buffer.

5. The processing system of claim 1 , wherein the return address verification logic is further configured, responsive to receiving a return address buffer pointer modification instruction, to perform at least one of: increment the return address buffer pointer or decrement the return address buffer pointer.

6. The processing system of claim 5 , wherein the return address buffer pointer modification instruction is a privileged instruction.

7. The processing system of claim 1 , wherein the stack is residing within a memory communicatively coupled to the processing system.

8. The processing system of claim 1 , wherein the return address buffer is at least partially residing within a memory incorporated into the processing system.

9. The processing system of claim 1 , wherein the return address buffer comprises a first portion residing within a memory incorporated into the processing system and a second portion residing within an external memory.

10. The processing system of claim 9 , wherein the external memory is provided by a read-only memory.

11. The processing system of claim 9 , wherein the second portion is configured to operate as an overflow buffer relatively to the first portion.

12. A method, comprising:
initializing a return address buffer pointer to point to an internal return address buffer;
modifying, by a processing system, a stack pointer;
modifying the return address buffer pointer;
responsive to determining that a boundary of the internal return address buffer is reached, causing the return address buffer pointer to point to an external return address buffer;
responsive to receiving a return instruction, comparing a first return address referenced by the stack pointer to a second return address referenced by the return address buffer pointer; and
executing the return instruction responsive to determining that the first return address is equal to the second return address.

13. The method of claim 12 , further comprising generating a stack fault exception responsive to determining that the first return address differs from the second return address.

14. The method of claim 12 , further comprising storing a return address on the stack and in the return address buffer responsive to receiving a call instruction.

15. The method of claim 12 , further comprising:
receiving a return address buffer modification instruction; and
performing at least one of: storing a return address in the return address buffer or removing a return address from the return address buffer.

16. The method of claim 12 , further comprising: responsive to receiving a return address buffer pointer modification instruction, performing at least one of: incrementing the return address buffer pointer or decrementing the return address buffer pointer.

17. A computer-readable non-transitory storage medium comprising executable instructions that, when executed by a processing system, cause the processing system to perform operations, comprising:
initializing a return address buffer pointer to point to an internal return address buffer;
modifying a stack pointer;
modifying the return address buffer pointer;
responsive to determining that a boundary of the internal return address buffer is reached, causing the return address buffer pointer to point to an external return address buffer;
responsive to receiving a return instruction, comparing a first return address referenced by the stack pointer to a second return address referenced by a return address buffer pointer; and
executing the return instruction responsive to determining that the first return address is equal to the second return address.

18. The computer-readable non-transitory storage medium of claim 17 , further comprising executable instructions causing the processing system to generate a stack fault exception responsive to determining that the first return address differs from the second return address.

19. The computer-readable non-transitory storage medium of claim 17 , further comprising executable instructions causing the processing system to store a return address on the stack and in the return address buffer responsive to receiving a call instruction.

20. The computer-readable non-transitory storage medium of claim 17 , further comprising executable instructions causing the processing system to:
receive a return address buffer modification instruction; and
perform at least one of: storing a return address in the return address buffer or removing a return address from the return address buffer.

Assignees

• Gerzon Gideon
• Stark Jared W
• Diskin Gal
• Intel Corp

Inventors

• Gerzon Gideon
• Stark Jared W
• Diskin Gal

Classifications

• G06F21/55 Primary

  Detecting local intrusion or implementing counter-measures · CPC title

• G06F21/52 Primary

  during program execution, e.g. stack integrity {; Preventing unwanted data erasure; Buffer overflow} · CPC title

• G06F12/1491

  in a hierarchical protection system, e.g. privilege levels, memory rings · CPC title

• G06F9/3861

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title

• G06F9/3806

  using address prediction, e.g. return stack, branch history buffer · CPC title