Virtual mode execution manager
US-12118376-B2 · Oct 15, 2024 · US
Efficient state transition among multiple programs on multi-threaded processors by executing cache priming program
US9015720B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9015720-B2 |
| Application number | US-34922709-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 6, 2009 |
| Priority date | Apr 30, 2008 |
| Publication date | Apr 21, 2015 |
| Grant date | Apr 21, 2015 |
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Abstract
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A system and method to optimize processor performance and minimizing average thread latency by selectively loading a cache when a program state, resources required for execution of a program or the program itself change, is described. An embodiment of the invention supports a “cache priming program” that is selectively executed for a first thread/program/sub-routine of each process. Such a program is optimized for situations when instructions and other program data are not yet resident in cache(s), and/or whenever resources required for program execution or the program itself changes. By pre-loading the cache with two resources required for two instructions for only a first thread, average thread latency is reduced because the resources are already present in the cache. Since, such a mechanism is carried out only for one thread in a program cycle, pitfalls of a conventional general pre-fetch scheme that involves parsing of the program in advance to determine which resources and instructions will be needed at a later time, are avoided.
First claim
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What is claimed is: 1. A method, comprising: determining whether an instruction sequence includes a first thread of a first normal program, wherein the first normal program comprises: a fetch of a first memory resource, a first instruction which, when executed, uses the first memory resource, a fetch of a second memory resource, and a second instruction which, when executed, uses the second memory resource; in response to the determining being positive, executing a cach…
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Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
- G06F9/4843Primary
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9015720B2 cover?
- A system and method to optimize processor performance and minimizing average thread latency by selectively loading a cache when a program state, resources required for execution of a program or the program itself change, is described. An embodiment of the invention supports a “cache priming program” that is selectively executed for a first thread/program/sub-routine of each process. Such a prog…
- Who is the assignee on this patent?
- Brown Andrew, Emberling Brian, Advanced Micro Devices Inc
- What technology area does this patent fall under?
- Primary CPC classification G06F9/4843. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Apr 21 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).