Automatic mutual exclusion
US-8930961-B2 · Jan 6, 2015 · US
Mapping vector representations onto a predicated scalar multi-threaded system
US9015656B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9015656-B2 |
| Application number | US-201313781285-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 28, 2013 |
| Priority date | Feb 28, 2013 |
| Publication date | Apr 21, 2015 |
| Grant date | Apr 21, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A system implementing a method for generating code for execution based on a SIMT model with parallel units of threads is provided. The system identifies a loop within a program that includes vector processing. The system generates instructions for a thread that include an instruction to set a predicate based on whether the thread of a parallel unit corresponds to a vector element. The system also generates instructions to perform the vector processing via scalar operations predicated on the predicate. As a result, the system generates instructions to perform the vector processing but to avoid branch divergence within the parallel unit of threads that would be needed to check whether a thread corresponds to a vector element.
First claim
Opening claim text (preview).
We claim: 1. A computer-readable storage memory containing computer-executable instructions for controlling a computer to generate code for execution based on a single-instruction multiple thread (“SIMT”) model with parallel units of threads, by a method comprising: determining whether a program includes vector processing; and upon determining that the program includes vector processing, generating instructions for a thread that include an instruction to set a predicate based on…
Assignees
Inventors
Classifications
- G06F9/30072Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
- G06F15/76Primary
Physics · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9015656B2 cover?
- A system implementing a method for generating code for execution based on a SIMT model with parallel units of threads is provided. The system identifies a loop within a program that includes vector processing. The system generates instructions for a thread that include an instruction to set a predicate based on whether the thread of a parallel unit corresponds to a vector element. The system al…
- Who is the assignee on this patent?
- Cray Inc
- What technology area does this patent fall under?
- Primary CPC classification G06F9/30072. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Apr 21 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).