Register file organization to share process context for heterogeneous multiple processors or joint processor

Patent metadata

Field	Value
Publication number	US-9015377-B2
Application number	US-201213692744-A
Country	US
Kind code	B2
Filing date	Dec 3, 2012
Priority date	Dec 30, 2011
Publication date	Apr 21, 2015
Grant date	Apr 21, 2015

Abstract

A register file organization is used to support multiple accesses from more than one processor or pipeline. This shared register file is organized for a multiple processor device that includes a high performance (HP) and a low power (LP) core. The shared register file includes separate HP and LP storage units coupled to separate HP and LP write and read ports.

First claim

We claim:

1. A multi-core device comprising:
a high performance (HP) core;
a low performance (LP) core; and
a shared register circuit coupled between said HP and LP cores and comprising
a HP write port coupled to the HP core,
a LP write port coupled to the LP core,
a HP storage unit coupled to the HP write port, and
a LP storage unit coupled to the LP write port,

wherein when in a LP mode, said HP core is idle, and all write operations from said LP core are stored in said LP storage unit,
wherein when in a HP mode, said LP core is idle, and all write operations from said HP core are stored in both said HP and LP storage units, and
wherein when transitioning from the LP mode to the HP mode, the stored data in said LP storage unit is copied to said HP storage unit.

2. The multi-core device of claim 1 wherein said shared register circuit comprises:
a HP read port coupled to the HP storage unit; and
a LP read port coupled to the LP storage unit.

3. The multi-core device of claim 1 wherein said HP storage unit comprises a plurality thereof coupled to the HP write port; and wherein said LP storage unit comprises a plurality thereof coupled to the LP write port.

4. The multi-core device of claim 3 further comprising:
a plurality of HP multiplexers coupled to the plurality of HP storage units; and
a plurality of LP multiplexers coupled to the plurality of LP storage units;
wherein said HP read port comprises a plurality thereof, each being coupled to a respective HP multiplexer of said plurality thereof; and
wherein said LP read port comprises a plurality thereof, each being coupled to a respective LP multiplexer of said plurality thereof.

5. The multi-core device of claim 1 wherein said HP storage unit and said LP storage unit each comprises a plurality of flip-flops.

6. A method of operating a multi-core device comprising a high performance (HP) core, a low performance (LP) core, and a shared register circuit coupled between the HP and LP cores and comprising a HP write port coupled to the HP core, a LP write port coupled to the LP core, a HP storage unit coupled to the HP write port, and a LP storage unit coupled to the LP write port, the method comprising:
operating the multi-core device while in a LP mode, so that the HP core is idle, and all write operations from the LP core are stored in the LP storage unit;
operating the multi-core device while in a HP mode, so that the LP core is idle, and all write operations from the HP core are stored in both the HP and LP storage units; and
operating the multi-core device to transition from the LP mode to the HP mode and so that the stored data in the LP storage unit is copied to the HP storage unit.

7. The method of claim 6 wherein the shared register circuit comprises:
a HP read port coupled to the HP storage unit; and
a LP read port coupled to the LP storage unit.

8. The method of claim 7 wherein the HP storage unit comprises a plurality thereof coupled to the HP write port; and wherein the LP storage unit comprises a plurality thereof coupled to the LP write port.

9. The method of claim 8 wherein the multi-core device further comprises:
a plurality of HP multiplexers coupled to the plurality of HP storage units;
a plurality of LP multiplexers coupled to the plurality of LP storage units;
wherein the HP read port comprises a plurality thereof, each being coupled to a respective HP multiplexer of the plurality thereof; and
wherein the LP read port comprises a plurality thereof, each being coupled to a respective LP multiplexer of the plurality thereof.

10. The method of claim 6 wherein the HP storage unit and the LP storage unit each comprises a plurality of flip-flops.

11. A non-transitory computer-readable medium having instructions stored thereon which, when executed by a multi-core device, cause the multi-core device to perform a method for operating, the multi-core device comprising a high performance (HP) core, a low performance (LP) core, and a shared register circuit coupled between the HP and LP cores and comprising a HP write port coupled to the HP core, a LP write port coupled to the LP core, a HP storage unit coupled to the HP write port, and a LP storage unit coupled to the LP write port, the method comprising:
operating the multi-core device while in a LP mode, so that the HP core is idle, and all write operations from the LP core are stored in the LP storage unit;
operating the multi-core device while in a HP mode, so that the LP core is idle, and all write operations from the HP core are stored in both the HP and LP storage units; and
operating the multi-core device to transition from the LP mode to the HP mode and so that the stored data in the LP storage unit is copied to the HP storage unit.

12. The non-transitory computer-readable medium of claim 11 wherein the shared register circuit comprises:
a HP read port coupled to the HP storage unit; and
a LP read port coupled to the LP storage unit.

13. The non-transitory computer-readable medium of claim 12 wherein the HP storage unit comprises a plurality thereof coupled to the HP write port; and wherein the LP storage unit comprises a plurality thereof coupled to the LP write port.

14. The non-transitory computer-readable medium of claim 13 wherein the multi-core device further comprises:
a plurality of HP multiplexers coupled to the plurality of HP storage units;
a plurality of LP multiplexers coupled to the plurality of LP storage units;
wherein the HP read port comprises a plurality thereof, each being coupled to a respective HP multiplexer of the plurality thereof; and
wherein the LP read port comprises a plurality thereof, each being coupled to a respective LP multiplexer of the plurality thereof.

15. The non-transitory computer-readable medium of claim 11 wherein the HP storage unit and the LP storage unit each comprises a plurality of flip-flops.

16. A shared register circuit in a multi-core device and coupled between a high performance (HP) core, and a low performance (LP) core, the shared register circuit comprising:
a HP write port coupled to the HP core;
a LP write port coupled to the LP core;
a HP storage unit coupled to the HP write port;
a LP storage unit coupled to the LP write port;
wherein when in a LP mode, said HP core is idle, and all write operations from said LP core are stored in said LP storage unit;
wherein when in a HP mode, said LP core is idle, and all write operations from said HP core are stored in both said HP and LP storage units; and
wherein when transitioning from the LP mode to the HP mode, the stored data in said LP storage unit is copied to said HP storage unit.

17. The shared register circuit of claim 16 wherein said shared register circuit comprises:
a HP read port coupled to the HP storage unit; and
a LP read port coupled to the LP storage unit.

18. The shared register circuit of claim 17 wherein said HP storage unit comprises a plurality thereof coupled to the HP write port; and wherein said LP storage unit comprises a plurality thereof coupled to the LP write port.

19. The shared register circuit of claim 18 further comprising:
a plurality of HP multiplexers coupled to the plurality of HP storage units; and
a plurality of LP multiplexers coupled to the plurality of LP storage units;
wherein said HP read port comprises a plurality thereof, each being coupled to a respective HP multiplexer of said plurality thereof; and
wherein said LP read port comprises a plurality thereof, each being coupled to a respe

Assignees

• Stmicroelectronics Beijing R & D Company Ltd
• St Microelectronics Srl
• Stmicroelectronics Bejing R & D Company Ltd
• St Microelectronics Srl

Inventors

• Wu Yongqiang
• Zhu Pengfei
• Sun Hongxia
• Guidetti Elio

Classifications

• G06F9/3012 Primary

  Organisation of register space, e.g. banked or distributed register file · CPC title

• G06F12/0802 Primary

  Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches · CPC title

• G06F9/30098

  Register arrangements · CPC title

• G06F9/30141

  Implementation provisions of register files, e.g. ports · CPC title