Technologies for dividing work across accelerator devices
US-2024143410-A1 · May 2, 2024 · US
US9014497B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9014497-B2 |
| Application number | US-201013994070-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 14, 2010 |
| Priority date | Dec 14, 2010 |
| Publication date | Apr 21, 2015 |
| Grant date | Apr 21, 2015 |
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A tile of pixels is encoded by variable length encoding at least a first block of pixels into a first sequence of symbols and a second block of pixels into a second sequence of symbols. The symbols of the first and second sequences are co-organized into a combined sequence of symbols in which the symbols of the first sequence are readable in a first reading direction and at least a portion of the symbols in the second sequence are readable in a second, opposite reading direction. The encoding of the tile to form one or more combined sequences significantly reduces the bandwidth requirements when writing the tile to a pixel value buffer. The co-organization of the first and second sequences enables parallel reading and decoding of the first and second sequences from the pixel value buffer, thereby reducing any decoding latency.
Opening claim text (preview).
The invention claimed is: 1. A method of encoding a tile of pixels each having a respective pixel value, said method comprising: variable length encoding a first block of pixels constituting a first subset of said tile to form a first sequence of symbols as an encoded representation of pixel values of said pixels in said first block and ii) a second block of pixels constituting a second subset of said tile to form a second sequence of symbols as an encoded representation of pixel…
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