Error signature analysis for data and clock recovery in a communication system

US9014313B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9014313-B2
Application numberUS-201213368314-A
CountryUS
Kind codeB2
Filing dateFeb 7, 2012
Priority dateFeb 7, 2012
Publication dateApr 21, 2015
Grant dateApr 21, 2015

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Abstract

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Described embodiments recover timing and data information from a signal received via a communication channel. An analog-to-digital converter (ADC) operating at a baud rate of the communication channel generates an actual ADC value corresponding to each bit sample of the received signal. A fast symbol estimation module estimates, based on the actual ADC value, a bit value corresponding to each bit sample. The fast symbol estimation module operates at a digital clock rate. The estimated bit values are provided to a timing recovery module. An ADC reconstruction module, based on a first number of pre-cursor estimated bit values, an estimated cursor bit value, and a second number of post-cursor estimated bit values, generates a reconstructed ADC value corresponding to each bit sample. Based on the reconstructed ADC values, the estimated bit values, and the actual ADC values, a corrected bit value is generated for each bit sample.

First claim

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We claim: 1. A method of recovering timing and data information from a signal received by a receiver of a communication system via a communication channel, the method comprising: generating, by an analog-to-digital converter (ADC) of the receiver, the ADC operating at a baud rate of the communication channel, W actual ADC values, each actual ADC value corresponding to a bit sample of a window of W bit samples of the received signal, wherein W is a positive integer; estimating, b…

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What does patent US9014313B2 cover?
Described embodiments recover timing and data information from a signal received via a communication channel. An analog-to-digital converter (ADC) operating at a baud rate of the communication channel generates an actual ADC value corresponding to each bit sample of the received signal. A fast symbol estimation module estimates, based on the actual ADC value, a bit value corresponding to each b…
Who is the assignee on this patent?
Chmelar Erik V, Lsi Corp
What technology area does this patent fall under?
Primary CPC classification H04L25/03057. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 21 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).