Semiconductor ESD circuit and method

Patent metadata

Field	Value
Publication number	US-9013842-B2
Application number	US-98765811-A
Country	US
Kind code	B2
Filing date	Jan 10, 2011
Priority date	Jan 10, 2011
Publication date	Apr 21, 2015
Grant date	Apr 21, 2015

Abstract

In an embodiment, an electrostatic discharge (ESD) circuit for providing protection between a first node and a second node includes a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node. The ESD circuit also includes a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node, a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, a second capacitor coupled between a gate of the second MOS device and the first node, and a second resistor coupled between the gate of the second MOS device and the second node.

First claim

What is claimed is:

1. An electrostatic discharge (ESD) circuit for providing protection between a first node and a second node, the ESD circuit comprising:
a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node;
a first capacitor coupled between a gate of the first MOS device and the first node;
a first resistor coupled between the gate of the first MOS device and the intermediate node;
a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, wherein the second source/drain of the first MOS device and the first source/drain of the second MOS device comprise a first common source/drain region and form a first stacked device unit, such that an ESD current flows primarily though a first parasitic bipolar device coupled between the first and second source/drain of the first MOS device and through a second parasitic bipolar device coupled between the first source/drain of the second MOS device and the second source/drain of the second MOS device;
a second capacitor coupled between a gate of the second MOS device and the first node; and
a second resistor coupled between the gate of the second MOS device and the second node, and
a second stacked device unit disposed adjacent to the first stacked device unit such that the second source/drain of the second MOS device of the first stacked device unit and the second source/drain of the second MOS device of the second stacked device unit form a second common source/drain region such that ESD current further flows through a third parasitic bipolar device coupled between the first source/drains of the first MOS devices of the first and second stacked device units and the second common source/drain region.

2. The ESD circuit of claim 1 , wherein:
the first capacitor comprises a first capacitance; and
the second capacitor comprises a series combination of two capacitors of a second capacitance.

3. The ESD circuit of claim 1 , wherein an RC time constant of the first capacitor and the first resistor is between about 10 ns and 1000 ns.

4. The ESD circuit of claim 1 , wherein the first MOS device and the second MOS device comprise low voltage NMOS devices.

5. The ESD circuit of claim 1 , wherein the first MOS device and the second MOS device comprise separately laid out devices such that an ESD current flows primarily through a channel of the first MOS device and a channel of the second MOS device.

6. The ESD circuit of claim 1 , wherein at least a portion of the first common source/drain region of the first stacked device unit does not have silicide disposed over it.

7. A semiconductor circuit comprising:
an ESD device region disposed within a semiconductor body of a first semiconductor type;
a first source/drain region of a second semiconductor type, the second semiconductor type opposite the first semiconductor type;
a first gate region disposed adjacent to the first source/drain region;
a second source/drain region of the second semiconductor type disposed adjacent to the first gate region, the first source/drain region, second source/drain region, and first gate region forming a first MOS device disposed with the ESD device region;
a third source/drain region of the second semiconductor type coupled to the second source/drain region;
a second gate region disposed adjacent to the third source/drain region;
a fourth source/drain region of the second semiconductor type disposed adjacent to the second gate region, the third source/drain region, fourth source/drain region, and second gate region forming a second MOS device disposed within the ESD device region;
a first capacitor coupled between the first source/drain region and the first gate region;
a first resistor coupled between the first gate region and the second source/drain region;
a second capacitor coupled between the first source/drain region and the second gate region; and
a second resistor coupled between the second gate region and fourth source/drain region.

8. The semiconductor circuit of claim 7 , wherein the first, second, third and fourth source/drain regions are covered with silicide.

9. The semiconductor circuit of claim 7 , wherein the first, second, third and fourth source/drain regions each comprise a portion that is not covered with silicide.

10. The semiconductor circuit of claim 7 , wherein:
the first semiconductor type is p-type;
the second semiconductor type is n-type; and
the first and second MOS devices comprise NMOS devices.

11. The semiconductor circuit of claim 10 , wherein the first and second MOS devices comprise low voltage NMOS devices.

12. The semiconductor circuit of claim 7 , wherein the second source/drain region and the third source/drain region comprise a shared source/drain region.

13. The semiconductor circuit of claim 7 , further comprising
a fifth source/drain region of the second semiconductor type;
a third gate region disposed adjacent to the fifth source/drain region;
a sixth source/drain region of the second semiconductor type disposed adjacent to the third gate region, the fifth source/drain region, sixth source/drain region, and third gate region forming a third MOS device disposed with the ESD device region;
a fourth gate region disposed adjacent to the sixth source/drain region;
a seventh source/drain region of the second semiconductor type disposed adjacent to the fourth gate region, the sixth source/drain region, seventh source/drain region, and fourth gate region forming a fourth MOS device disposed within the ESD device region, wherein
the fifth source/drain region is coupled to the first source/drain region; and
the seventh source/drain region and the fourth source/drain region form a shared source/drain region.

14. The semiconductor circuit of claim 13 , wherein the first, second, third, fourth, fifth, sixth and seventh source/drain regions each comprise a portion that is not covered with silicide.

15. The semiconductor circuit of claim 13 , further comprising a first guard ring surrounding the ESD device region, the first guard ring comprising a doped region of the first semiconductor type.

16. The semiconductor circuit of claim 15 , further comprising a second guard ring surrounding the first guard ring, the second guard ring comprising a doped region of the second semiconductor type.

17. A method of operating a semiconductor circuit, the method comprising:
providing a protection device between a first and second protected node, the first and second protected node being coupled to circuitry in a semiconductor substrate, the protection device comprising
a first MOS device having a first source/drain coupled to the first protected node, and a second source/drain coupled to an intermediate node,
a first capacitor coupled between a gate of the first MOS device and the first protected node,
a first resistor coupled between the gate of the first MOS device and the intermediate node,
a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second protected node,
a second capacitor coupled between a gate of the second MOS device and the first protected node, and
a second resistor coupled between the gate of the second MOS device and the second protected node; and

protecting the circuitry from a fast transient voltage on the first protected node, protecting comprising
coupling the fast transient voltage to the gate of the first MOS device via the first capacitor,
coupling

Assignees

• Domanski Krzysztof
• Soldner Wolfgang
• Russ Cornelius Christian
• Alvarez David
• Ille Adrien
• Infineon Technologies Ag

Inventors

• Domanski Krzysztof
• Soldner Wolfgang
• Russ Cornelius Christian
• Alvarez David
• Ille Adrien

Classifications

• H10D62/371

  Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current · CPC title

• H10D62/126

  Top-view geometrical layouts of the regions or the junctions · CPC title

• H10D89/819

  Bias arrangements for gate electrodes of FETs, e.g. RC networks or voltage partitioning circuits (FETs in a Darlington configuration H10D89/817) · CPC title

• H02H9/046 Primary

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title

• H01L29/0692

  Electricity · mapped topic