Track and hold architecture with tunable bandwidth

Patent metadata

Field	Value
Publication number	US-9013339-B2
Application number	US-201213551950-A
Country	US
Kind code	B2
Filing date	Jul 18, 2012
Priority date	Aug 17, 2010
Publication date	Apr 21, 2015
Grant date	Apr 21, 2015

Abstract

To date, bandwidth mismatch within time-interleaved (TI) analog-to-digital converters (ADCs) has been largely ignored because compensation for bandwidth mismatch is performed by digital post-processing, namely finite impulse response filters. However, the lag from digital post-processing is prohibitive in high speed systems, indicating a need for blind mismatch compensation. Even with blind bandwidth mismatch estimation, though, adjustment of the filter characteristics of track-and-hold (T/H) circuits within the TI ADCs can be difficult. Here, a T/H circuit architecture is provided that uses variations of the gate voltage of a sampling switch (which varies the “on” resistance of the sampling switch) to change the bandwidth of the T/H circuits so as to precisely match the bandwidths.

First claim

The invention claimed is:

1. An apparatus comprising:
a clock divider that receives a clock signal;
a plurality analog-to-digital converter (ADC) branches that each receive an analog input signal, wherein each ADC branch includes:
a delay circuit that is coupled to the clock divider;
an ADC having:
a bootstrap circuit that is coupled to the delay circuit;
a sampling switch that is coupled to the bootstrap circuit; and
a controller that is coupled to the bootstrap circuit…

Assignees

• Payne Robert F
• Corsi Marco
• Texas Instruments Inc

Inventors

• Payne Robert F
• Corsi Marco

Classifications

• H03M1/08 Primary

  Electricity · mapped topic

• H03M1/1215

  Electricity · mapped topic