Integrated circuit with electrostatic discharge protection
US-2024395801-A1 · Nov 28, 2024 · US
Semiconductor device including ESD protection device
US9012997B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9012997-B2 |
| Application number | US-201213661683-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 26, 2012 |
| Priority date | Oct 26, 2012 |
| Publication date | Apr 21, 2015 |
| Grant date | Apr 21, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
A semiconductor device includes a semiconductor-on-insulator (SOI) substrate having a bulk substrate layer, an active semiconductor layer and a buried insulator layer disposed between the bulk substrate layer and the active semiconductor layer. A trench is formed through the SOI substrate to expose the bulk substrate layer. A doped well is formed in an upper region of the bulk substrate layer adjacent trench. The semiconductor device further includes a first doped region different from the doped well that is formed in the trench.
First claim
Opening claim text (preview).
The invention claimed is: 1. A semiconductor device, comprising: a semiconductor-on-insulator (SOI) substrate including a bulk substrate layer, an active semiconductor layer and a buried insulator layer disposed between the bulk substrate layer and the active semiconductor layer; a trench formed through the active semiconductor layer and the buried insulator layer of the SOI substrate to expose the bulk substrate layer; a doped well formed in an upper region of the bulk substr…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9012997B2 cover?
- A semiconductor device includes a semiconductor-on-insulator (SOI) substrate having a bulk substrate layer, an active semiconductor layer and a buried insulator layer disposed between the bulk substrate layer and the active semiconductor layer. A trench is formed through the SOI substrate to expose the bulk substrate layer. A doped well is formed in an upper region of the bulk substrate layer a…
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification H10D89/611. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 21 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).