Array substrate and manufacturing method thereof
US-12185597-B2 · Dec 31, 2024 · US
Thin film transistor array panel and method for manufacturing the same
US9012994B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9012994-B2 |
| Application number | US-201314012580-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 28, 2013 |
| Priority date | May 8, 2013 |
| Publication date | Apr 21, 2015 |
| Grant date | Apr 21, 2015 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
A thin film transistor array panel is disclosed. The thin film transistor array panel may include a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, a data wiring layer disposed on the substrate and including a data line crossing the gate line, a source electrode connected to the data line and a drain electrode facing the source electrode, a polymer layer covering the source electrode and the drain electrode, and a passivation layer disposed on the polymer layer. The data wiring layer may include copper or a copper alloy and the polymer layer may include fluorocarbon.
First claim
Opening claim text (preview).
What is claimed is: 1. A thin film transistor array panel, comprising: a gate line disposed on a substrate, the gate line comprising a gate electrode; a semiconductor layer comprising an oxide semiconductor, the semiconductor layer disposed on the substrate; a data wiring layer disposed on the substrate, the data wiring layer comprising a data line crossing the gate line a source electrode connected to the data line and a drain electrode facing the source electrode; a polyme…
Assignees
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Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10D86/60Primary
Electricity · mapped topic
- H10D86/441Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9012994B2 cover?
- A thin film transistor array panel is disclosed. The thin film transistor array panel may include a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, a data wiring layer disposed on the substrate and including a data line crossing the gate line, a source electrode connected to the data line and a d…
- Who is the assignee on this patent?
- Samsung Display Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10D86/60. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 21 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).