Semiconductor device

US9012959B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9012959-B2
Application numberUS-201414198763-A
CountryUS
Kind codeB2
Filing dateMar 6, 2014
Priority dateJun 4, 2013
Publication dateApr 21, 2015
Grant dateApr 21, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device includes: a semiconductor substrate having an upper surface and a lower surface; a field effect transistor having a semiconductor layer on the upper surface of the semiconductor substrate, a gate electrode, a drain electrode, and a source electrode; a P-type diffusion region in the semiconductor substrate and extending to the upper surface of the semiconductor substrate; a first N-type diffusion region in the semiconductor substrate and extending t the upper surface of the semiconductor substrate; a first connection electrode connecting the P-type diffusion region to a grounding point; and a second connection electrode connecting the first N-type diffusion region to the gate electrode or the drain electrode. The P-type diffusion region and the first N-type diffusion region constitute a bidirectional lateral diode.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device comprising: a semiconductor substrate having an upper surface and a lower surface; a field effect transistor having a semiconductor layer on the upper surface of the semiconductor substrate, a gate electrode, a drain electrode, and a source electrode; a P-type diffusion region in the semiconductor substrate and extending to the upper surface of the semiconductor substrate; a first N-type diffusion region in the semiconductor subs…

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Frequently asked questions

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What does patent US9012959B2 cover?
A semiconductor device includes: a semiconductor substrate having an upper surface and a lower surface; a field effect transistor having a semiconductor layer on the upper surface of the semiconductor substrate, a gate electrode, a drain electrode, and a source electrode; a P-type diffusion region in the semiconductor substrate and extending to the upper surface of the semiconductor substrate; …
Who is the assignee on this patent?
Mitsubishi Electric Corp
What technology area does this patent fall under?
Primary CPC classification H10D8/051. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 21 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).