Thin film transistor, array substrate, and display apparatus

US9012906B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9012906-B2
Application numberUS-201213688222-A
CountryUS
Kind codeB2
Filing dateNov 29, 2012
Priority dateSep 21, 2012
Publication dateApr 21, 2015
Grant dateApr 21, 2015

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

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A thin film transistor disposed on a substrate is provided. The TFT includes a gate layer, an insulation layer, a carrier transmission layer, a passivation layer, a first source/drain layer, and a second source/drain layer. The gate layer is disposed on the substrate. The insulation layer is disposed on the gate layer. The carrier transmission layer is disposed on the insulation layer. The carrier transmission layer includes an active layer and a mobility enhancement layer. The passivation layer is disposed on the active layer. The first source/drain layer is disposed on the active layer. The second source/drain layer is disposed on the active layer. The mobility enhancement layer includes a first element. The active layer includes a second element. The electronegativity of the first element is smaller than that of the second element to enhance the carrier mobility of the active layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A thin film transistor adapted to be arranged on a substrate, the thin film transistor comprising: a gate layer disposed on the substrate; an insulation layer disposed on the gate layer; a carrier transmission layer disposed on the insulation layer and comprising an active layer and a mobility enhancement layer; a passivation layer disposed on the active layer; a first source/drain layer disposed on the active layer and connected with the active laye…

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What does patent US9012906B2 cover?
A thin film transistor disposed on a substrate is provided. The TFT includes a gate layer, an insulation layer, a carrier transmission layer, a passivation layer, a first source/drain layer, and a second source/drain layer. The gate layer is disposed on the substrate. The insulation layer is disposed on the gate layer. The carrier transmission layer is disposed on the insulation layer. The carr…
Who is the assignee on this patent?
E Ink Holdings Inc
What technology area does this patent fall under?
Primary CPC classification H10D30/6755. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 21 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).