Scan-based reset

Patent metadata

Field	Value
Publication number	US-9009552-B2
Application number	US-87869310-A
Country	US
Kind code	B2
Filing date	Sep 9, 2010
Priority date	Sep 9, 2010
Publication date	Apr 14, 2015
Grant date	Apr 14, 2015

Abstract

Scan-based reset utilizes already existing design-for-test scan chains to reset control and logic circuitry upon reset conditions, such as power-up reset. Such utilization eliminates the need for expensive, high fan-out reset trees and per scan cell reset control logic, thus reducing chip area and power consumption. Additional power savings is achieved by controlling clock frequency during reset conditions. Limiting scan cell chain length and providing multiple chains reduces reset latency.

First claim

We claim:

1. A method of resetting a semiconductor device comprising:
sensing a reset condition; and
shifting reset data for non-test operation of the semiconductor device through a scan chain in response to the reset condition, wherein each element of the scan chain comprises a scannable sequential element configured to receive only a data input, a scan input, a scan enable input, and a clock input, and the reset data is received by the scan input of one of the scannable sequen…

Assignees

• Kwan Bill K
• Gorti Atchyuth K
• Pandey Amit Raj
• Kuchipudi Venkat K
• Jagirdar Aditya
• Advanced Micro Devices Inc

Inventors

• Kwan Bill K
• Gorti Atchyuth K
• Pandey Amit Raj
• Kuchipudi Venkat K
• Jagirdar Aditya

Classifications

• G01R31/318575 Primary

  Physics · mapped topic