Shared memory space in a unified memory model

Patent metadata

Field	Value
Publication number	US-9009419-B2
Application number	US-201213562985-A
Country	US
Kind code	B2
Filing date	Jul 31, 2012
Priority date	Jul 31, 2012
Publication date	Apr 14, 2015
Grant date	Apr 14, 2015

Abstract

Methods and systems are provided for mapping a memory instruction to a shared memory address space in a computer arrangement having a CPU and an APD. A method includes receiving a memory instruction that refers to an address in the shared memory address space, mapping the memory instruction based on the address to a memory resource associated with either the CPU or the APD, and performing the memory instruction based on the mapping.

First claim

What is claimed is:

1. A method of mapping a memory instruction to a shared memory address space in a computer arrangement configured for unified operation between a central processing unit (CPU) and an accelerated processing device (APD), comprising:
receiving the memory instruction, wherein the memory instruction refers to an address in the shared memory address space;
mapping the memory instruction to a memory resource based on the address, wherein the memory resource is associated with at least one of the CPU and the APD; and
sending information corresponding to the mapping to the CPU or APD.

2. The method of claim 1 , wherein the memory instruction is received from the APD.

3. The method of claim 2 , wherein when the mapping maps to a private memory resource associated with the APD, the mapping comprises, using a video memory manager to map the memory instruction to the private memory resource.

4. The method of claim 2 , wherein when the mapping maps to a shared memory resource associated with the APD, the mapping comprises using a system memory manager to map the memory instruction to the shared memory resource, wherein the shared memory resource is accessible by both the CPU and the APD.

5. The method of claim 2 , wherein when the mapping maps to a shared memory resource associated with the CPU, the mapping comprises using a system memory manager to map the memory instruction to the shared memory resource, wherein the shared memory resource is accessible by both the CPU and the APD.

6. The method of claim 1 , wherein the memory instruction is received from a CPU.

7. The method of claim 6 , wherein when the mapping maps to a shared memory resource associated with the APD, the mapping comprises using a system memory manager to map the memory instruction to the shared memory resource, wherein the shared memory resource is accessible by both the CPU and APD.

8. The method of claim 6 , wherein when the mapping maps to a private memory resource associated with the CPU, the mapping comprises using a CPU memory manager to map the memory instruction to the private memory resource, wherein the private memory resource is not accessible by the APD.

9. The method of claim 1 , wherein the CPU and APD both perform instructions in an application.

10. The method of claim 5 , wherein an operating system memory manager manages the CPU memory manager and the system memory manager.

11. A system for mapping a memory instruction to a shared memory address space in a computer arrangement configured for unified operation between a central processing unit (CPU) or an accelerated processing device (APD), comprising:
a memory instruction receiver, configured to receive the memory instruction, the memory instruction referring to an address in the shared memory address space;
a memory selector configured to select a memory resource based on the address, wherein the memory resource is associated with the CPU or the APD; and
a memory instruction mapper configured to map the memory instruction to the selected memory resource based on the memory instruction, wherein the memory instruction is performed based on the mapping.

12. The system of claim 11 , wherein the memory instruction is received from the APD.

13. The system of claim 12 , wherein when the selected memory resource is a private memory resource associated with the APD, the mapping comprises, using a video memory manager to map the memory instruction to the private memory resource.

14. The system of claim 12 , wherein when the selected memory resource is a shared memory resource associated with the APD, the mapping comprises using a system memory manager to map the memory instruction to the shared memory resource, wherein the shared memory resource is accessible by both the CPU and the APD.

15. The system of claim 12 , wherein when the selected memory resource is a shared memory resource associated with the CPU, the mapping comprises using a system memory manager to map the memory instruction to the shared memory resource, wherein the shared memory resource is accessible by both the CPU and the APD.

16. The system of claim 11 , wherein the memory instruction is received from the CPU.

17. The system of claim 16 , wherein when the selected memory resource is a shared memory resource associated with the APD, the mapping comprises using a system memory manager to map the memory instruction to the shared memory resource, wherein the shared memory resource is accessible by the CPU and the APD.

18. The system of claim 16 , wherein when the selected memory resource is a private memory resource associated with the CPU, the mapping comprises using a CPU memory manager to map the memory instruction to the private memory resource, wherein the private memory resource is not accessible by the APD.

19. The system of claim 11 , wherein the CPU and APD both perform instructions in an application.

20. The method of claim 14 , wherein an operating system memory manager manages the CPU memory manager and the system memory manager.

21. A central processing unit (CPU) configured to map a memory instruction to a shared memory address space, comprising:
a memory instruction receiver, configured to receive the memory instruction, the memory instruction referring to an address in the shared memory address space;
a memory selector configured to select a memory resource based on the address, wherein the memory resource is associated with the CPU or an accelerated processing device (APD); and
a memory instruction mapper configured to map the memory instruction to the selected memory resource based on the memory instruction, wherein the memory instruction is performed based on the mapping.

22. The CPU of claim 21 , wherein the memory instruction is received from the APD.

23. The CPU of claim 21 , wherein the memory instruction is received from the CPU.

24. An accelerated processing device (APD) configured to map a memory instruction to a shared memory address space, comprising:
a memory instruction receiver, configured to receive the memory instruction, the memory instruction referring to an address in the shared memory address space;
a memory selector configured to select a memory resource based on the address, wherein the memory resource is associated with a central processing unit (CPU) or the APD; and
a memory instruction mapper configured to map the memory instruction to the selected memory resource based on the memory instruction, wherein the memory instruction is performed based on the mapping.

25. The APD of claim 24 , wherein the memory instruction is received from the APD.

26. The APD of claim 24 , wherein the memory instruction is received from the CPU.

Assignees

• Asaro Anthony
• Normoyle Kevin
• Hummel Mark D
• Fowler Mark
• Advanced Micro Devices Inc
• Ati Technologies Ulc

Inventors

• Asaro Anthony
• Normoyle Kevin
• Hummel Mark D
• Fowler Mark

Classifications

• G06F12/0292 Primary

  using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10) · CPC title

• G06F12/06

  Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (G06F12/08 takes precedence) · CPC title

• G06F12/063 Primary

  for I/O modules, e.g. memory mapped I/O (I/O protocol G06F13/42) · CPC title