Selectively Connecting a Port of an Electrical Device to Components in the Electrical Device
US-2015363344-A1 · Dec 17, 2015 · US
Method and apparatus for minimizing within-die variations in performance parameters of a processor
US9009366B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9009366-B2 |
| Application number | US-201414225375-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 25, 2014 |
| Priority date | Mar 29, 2010 |
| Publication date | Apr 14, 2015 |
| Grant date | Apr 14, 2015 |
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Abstract
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Described herein are a method and an apparatus for minimizing within-die variations in performance parameters of a processor. The apparatus comprising: a reference generator to generate an adjustable compensated reference signal; a bias generator to generate a bias signal based on the adjustable compensated reference signal; a transmitter coupled with the bias generator to transmit an output signal; and a feedback mechanism to sample the output signal from the transmitter and to provide the sampled output signal to the bias generator.
First claim
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We claim: 1. An apparatus comprising: a reference generator to generate an adjustable compensated reference signal; a bias generator to generate a bias signal based on the adjustable compensated reference signal; a transmitter coupled with the bias generator to transmit an output signal; and a feedback mechanism to sample the output signal from the transmitter and to provide the sampled output signal to the bias generator. 2. The apparatus of claim 1 ,…
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Physics · mapped topic
- G06F13/122Primary
Physics · mapped topic
Physics · mapped topic
- H04L25/0274Primary
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9009366B2 cover?
- Described herein are a method and an apparatus for minimizing within-die variations in performance parameters of a processor. The apparatus comprising: a reference generator to generate an adjustable compensated reference signal; a bias generator to generate a bias signal based on the adjustable compensated reference signal; a transmitter coupled with the bias generator to transmit an output si…
- Who is the assignee on this patent?
- Intel Corp
- What technology area does this patent fall under?
- Primary CPC classification G06F13/122. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Apr 14 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).