Active level shift driver circuit and liquid crystal display apparatus including the same

Patent metadata

Field	Value
Publication number	US-9007291-B2
Application number	US-201113278042-A
Country	US
Kind code	B2
Filing date	Oct 20, 2011
Priority date	Oct 22, 2010
Publication date	Apr 14, 2015
Grant date	Apr 14, 2015

Abstract

An active level shift (ALS) driver circuit and a liquid crystal display apparatus including the ALS driver circuit are disclosed. The ALS driver circuit includes an input unit configured to apply a first polarity voltage to a first node and to apply a second polarity voltage to a second node, a level compensation unit configured to adjust the voltages of the first node and the second node, and an output unit configured to alternately output a first power voltage and a second power voltage according to the adjusted voltages of the first and second nodes.

First claim

What is claimed is:

1. An active level shift (ALS) driver comprising a plurality of ALS driving circuits, wherein each of the plurality of ALS driving circuits comprises:
an input unit configured to apply a first polarity voltage to a first node, and to apply a second polarity voltage to a second node;
a reset unit configured to apply an initial voltage to the first node and the second node, wherein the reset unit is configured to receive a reset signal;
a level compensation unit configured to compensate a voltage drop of the first node and the second node; and
an output unit configured to output a first power voltage or a second power voltage according to the initial voltage and then to alternately output the first power voltage and the second power voltage according to the first polarity voltage and the second polarity voltage,
wherein the ALS driver comprises only N-channel transistors or only P-channel transistors, and
wherein the input unit comprises:
a first transistor comprising a gate electrode electrically connected to a first input terminal to which a first input signal is applied, and a first electrode electrically connected to a first polarity terminal to which the first polarity voltage is applied;
a second transistor comprising a gate electrode electrically connected to the first input terminal, a first electrode electrically connected to a second electrode of the first transistor, and a second electrode electrically connected to a third node;
a third transistor comprising a gate electrode electrically connected to the first input terminal, a first electrode electrically connected to the third node, and a second electrode electrically connected to the first node;
a fourth transistor comprising a gate electrode electrically connected to the first input terminal, and a first electrode electrically connected to a second polarity terminal to which the second polarity voltage is applied;
a fifth transistor comprising a gate electrode electrically connected to the first input terminal, a first electrode electrically connected to a second electrode of the fourth transistor, and a second electrode electrically connected to a fourth node; and
a sixth transistor comprising a gate electrode electrically connected to the first input terminal, a first electrode electrically connected to the fourth node, and a second electrode electrically connected to the second node,
wherein the first polarity voltage and the second polarity voltage have opposite polarities.

2. The ALS driver of claim 1 , wherein the level compensation unit comprises:
a first level compensation unit configured to compensate the voltage of one of the first and second nodes; and
a second level compensation unit configured to compensate the voltage of one of the first and second nodes.

3. The ALS driver of claim 2 , wherein the first level compensation unit comprises:
a ninth transistor comprising a gate electrode electrically connected to a second input terminal, a first electrode electrically connected to a fourth power terminal, and a second electrode electrically connected to a third node; and
a tenth transistor comprising a gate electrode electrically connected to the second input terminal, a first electrode electrically connected to the fourth power terminal, and a second electrode electrically connected to a fourth node.

4. The ALS driver of claim 3 , wherein a second input signal applied to the second input terminal has a polarity opposite to that of a first input signal.

5. The ALS driver of claim 2 , wherein the second level compensation unit comprises:
an eighteenth transistor comprising a gate electrode electrically connected to the first node, and a first electrode electrically connected to a third power terminal;
a seventeenth transistor comprising a gate electrode electrically connected to the first node, a first electrode electrically connected to a second electrode of the eighteenth transistor, and a second electrode electrically connected to the second node;
a twentieth transistor comprising a gate electrode electrically connected to the second node, and a first electrode electrically connected to the third power terminal; and
a nineteenth transistor comprising a gate electrode electrically connected to the second node, a first electrode electrically connected to a second electrode of the twentieth transistor, and a second electrode electrically connected to the first node.

6. The ALS driver of claim 1 , wherein the first polarity voltage and the second polarity voltage are applied during an interval corresponding to a frame.

7. The ALS driver of claim 1 , wherein the reset unit in odd numbered ALS driving circuits of the plurality of ALS driving circuits applies a third power voltage to the first node and a fourth power voltage to the second node so as to output the second power voltage, and the reset unit in even numbered ALS driving circuits of the plurality of ALS driving circuits applies the fourth power voltage to the first node and the third power voltage to the second node so as to output the first power voltage.

8. The ALS driver of claim 1 , wherein each of the plurality of ALS driving circuits further comprises a boosting unit for increasing a potential of the first node or the second node, in response to a third input signal having a second level voltage being lower than a low voltage of a gate signal output from the gate driver, and increasing a driving current of the output unit.

9. The ALS driver of claim 1 , wherein the first input signal has voltage levels of a first level voltage being the low voltage of the gate signal and of a second level voltage.

10. The ALS driver of claim 1 , wherein the reset unit comprises:
a seventh transistor comprising a gate electrode electrically connected to a reset terminal, a first electrode electrically connected to a fourth power terminal, and a second electrode electrically connected to the first node; and
an eighth transistor comprising a gate electrode electrically connected to the reset terminal, a first electrode electrically connected to a third power terminal, and a second electrode electrically connected to the second node.

11. The ALS driver of claim 1 , wherein the reset unit comprises:
a seventh transistor comprising a gate electrode electrically connected to a reset terminal, a first electrode electrically connected to a third power terminal, and a second electrode electrically connected to the first node; and
an eighth transistor comprising a gate electrode electrically connected to the reset terminal, a first electrode electrically connected to a fourth power terminal, and a second electrode electrically connected to the second node.

12. The ALS driver of claim 1 , wherein the first power voltage is a high level voltage, and the second power voltage is a low level voltage.

13. An active level shift (ALS) driver comprising a plurality of ALS driving circuits, wherein each of the plurality of ALS driving circuits comprises:
an input unit configured to apply a first polarity voltage to a first node, and to apply a second polarity voltage to a second node in response to a first input signal having a voltage level being lower than a low voltage of a gate signal output from a gate driver;
a reset unit configured to apply an initial voltage to the first node and the second node, wherein the reset unit is configured to receive a reset signal;
a level compensation unit configured to compensate a voltage drop of the first node and the second node; and
an output unit configured to output a first power voltage or a second power voltage according to the initial voltage and then to alternate

Assignees

• Lee Seung-Kyu
• Lee Dong-Hoon
• Kim Chul-Ho
• Kim Kyung-Hoon
• Kim Se-Hyang
• Samsung Display Co Ltd

Inventors

• Lee Seung-Kyu
• Lee Dong-Hoon
• Kim Chul-Ho
• Kim Kyung-Hoon
• Kim Se-Hyang

Classifications

• H03K19/018507

  Interface arrangements · CPC title

• G09G3/3614

  Control of polarity reversal in general · CPC title

• G09G3/3655 Primary

  Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors · CPC title

• G09G2300/0876

  Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes · CPC title