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Successive-approximation-register analog-to-digital converter and method thereof
US9007253B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9007253-B2 |
| Application number | US-201314045821-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 4, 2013 |
| Priority date | Dec 21, 2011 |
| Publication date | Apr 14, 2015 |
| Grant date | Apr 14, 2015 |
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Abstract
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A main ADC (analog-to-digital converter) for converting an analog input signal into a digital data, and an auxiliary ADC for converting the same analog input signal into an auxiliary digital data, wherein: the main ADC is a successive-approximation-register (SAR) ADC of a first resolution with a first conversion speed; the auxiliary ADC is of a second resolution with a second conversion speed; the second resolution is lower than the first resolution but the second conversion speed is higher than the first conversion speed; and the main ADC generates the digital data by undergoing a process of successive approximation comprising a plurality of steps including a fast-track step that is based on a value of the auxiliary digital data.
First claim
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The invention claimed is: 1. An analog-to-digital conversion apparatus, comprising: a first ADC (analog-to-digital converter) having a first resolution and a first conversion speed, for converting an analog input signal into a first digital signal, based in part on a value of a second digital signal provided to the first ADC, the first ADC comprising: a bootstrapped controller, for updating a digital code according to a decision signal and the second digital signal and generating…
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- What does patent US9007253B2 cover?
- A main ADC (analog-to-digital converter) for converting an analog input signal into a digital data, and an auxiliary ADC for converting the same analog input signal into an auxiliary digital data, wherein: the main ADC is a successive-approximation-register (SAR) ADC of a first resolution with a first conversion speed; the auxiliary ADC is of a second resolution with a second conversion speed; …
- Who is the assignee on this patent?
- Realtek Semiconductor Corp
- What technology area does this patent fall under?
- Primary CPC classification H03M1/145. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 14 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).