Built-in self test circuit for measuring performance of clock data recovery and system-on-chip including the same
US-2024302432-A1 · Sep 12, 2024 · US
Integrated circuit
US9007115B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9007115-B2 |
| Application number | US-201414489618-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 18, 2014 |
| Priority date | Oct 28, 2011 |
| Publication date | Apr 14, 2015 |
| Grant date | Apr 14, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
An integrated circuit includes a clock control unit configured to selectively output an external clock or a delayed clock acquired by delaying the external clock as an input clock in response to a divided clock generated by dividing the external clock, when a test mode is entered; and an internal circuit operating in response to the input clock.
First claim
Opening claim text (preview).
What is claimed is: 1. An integrated circuit comprising: a clock control unit configured to transfer a first reference voltage or a second reference voltage as a first selection reference voltage in response to a divided clock which is generated by dividing an external clock when a test mode is entered, and generate an input clock by comparing the first selection reference voltage and the external clock; wherein the clock control unit comprises: a control signal generating s…
Assignees
Inventors
Classifications
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9007115B2 cover?
- An integrated circuit includes a clock control unit configured to selectively output an external clock or a delayed clock acquired by delaying the external clock as an input clock in response to a divided clock generated by dividing the external clock, when a test mode is entered; and an internal circuit operating in response to the input clock.
- Who is the assignee on this patent?
- Sk Hynix Inc
- What technology area does this patent fall under?
- Primary CPC classification H03K5/13. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 14 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).