Semiconductor device

Patent metadata

Field	Value
Publication number	US-9006830-B2
Application number	US-201314062019-A
Country	US
Kind code	B2
Filing date	Oct 24, 2013
Priority date	Oct 30, 2012
Publication date	Apr 14, 2015
Grant date	Apr 14, 2015

Abstract

Provided is a semiconductor device having high ESD tolerance. A first via ( 16 ) is used for electrically connecting a pad ( 22 ) to a drain of an NMOS transistor of an ESD protective circuit. The first vias ( 16 ) are formed under the pad ( 22 ) only on one side of a rectangular ring-shaped intermediate metal film ( 17 ) and on another side thereof opposed to the one side. In other words, all the first vias ( 16 ) for establishing an electrical connection to the drains are present substantially directly under the pad ( 22 ). Consequently, a surge current caused by ESD and applied to the pad ( 22 ) is more likely to flow uniformly among all the drains. Then, respective channels of the NMOS transistor of the ESD protective circuit are more likely to uniformly operate, and hence the ESD tolerance of the semiconductor device is increased.

First claim

What is claimed is:

1. A semiconductor device, comprising:
an NMOS transistor formed under a pad,
the NMOS transistor comprising:
a diffusion region for a source and a diffusion region for a drain, each alternately arranged;
a gate electrode disposed above each channel between the source and the drain; and
a P-type diffusion region for fixing a substrate potential, the P-type diffusion region surrounding the diffusion region for the source, the diffusion region for the drain…

Assignees

• Seiko Instr Inc

Inventors

• Koyama Takeshi
• Hirose Yoshitsugu

Classifications

• H10W20/484 Primary

  Electricity · mapped topic

• H10D64/257 Primary

  Electricity · mapped topic

• H10D89/601

  Electricity · mapped topic

• H01L2924/00

  Electricity · mapped topic

• H01L2924/0002

  Electricity · mapped topic