Nonvolatile memory device and method for fabricating the same

US9006089B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9006089-B2
Application numberUS-201414524545-A
CountryUS
Kind codeB2
Filing dateOct 27, 2014
Priority dateDec 29, 2011
Publication dateApr 14, 2015
Grant dateApr 14, 2015

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Abstract

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The technology of the present invention relates to a non-volatile memory device and a fabrication method thereof. The non-volatile memory device includes channel layers protruding vertically from a substrate, a plurality of hole-supply layers and a plurality of gate electrodes, which are alternately stacked along the channel layers, and a memory film interposed between the channel layers and the gate electrodes and between the hole-supply layers and the gate electrodes. According to this technology, the hole-supply layers are formed between the memory cells such that sufficient holes are supplied to the memory cells during the erase operation of the memory cells, whereby the erase operation of the memory cells is smoothly performed without using the GIDL current, and the properties of the device are protected from being deteriorated due to program/erase cycling.

First claim

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What is claimed is: 1. A method for fabricating a non-volatile memory device, comprising: forming an interlayer insulating film over a substrate; alternately stacking a plurality of hole-supply layers and a plurality of sacrificial layers over the interlayer insulating film; selectively etching the hole-supply layers and the sacrificial layers to form channel holes which expose the substrate; forming a channel layer in each of the channel holes; forming a slit hole through…

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What does patent US9006089B2 cover?
The technology of the present invention relates to a non-volatile memory device and a fabrication method thereof. The non-volatile memory device includes channel layers protruding vertically from a substrate, a plurality of hole-supply layers and a plurality of gate electrodes, which are alternately stacked along the channel layers, and a memory film interposed between the channel layers and th…
Who is the assignee on this patent?
Sk Hynix Inc
What technology area does this patent fall under?
Primary CPC classification H01L27/11582. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 14 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).