Continuity check monitoring for microchip exploitation detection

Patent metadata

Field	Value
Publication number	US-9003559-B2
Application number	US-18135708-A
Country	US
Kind code	B2
Filing date	Jul 29, 2008
Priority date	Jul 29, 2008
Publication date	Apr 7, 2015
Grant date	Apr 7, 2015

Abstract

Apparatus, method and program product detect an attempt to tamper with a microchip by determining that an electrical path comprising one or more connections and a metal plate attached to the backside of a microchip has become disconnected or otherwise altered. A tampering attempt may also be detected in response to the presence of an electrical path that should not be present, as may result from the microchip being incorrectly reconstituted. Actual and/or deceptive paths may be automatically selected and monitored to further confound a reverse engineering attempt.

First claim

What is claimed is:

1. An apparatus comprising:
an electrical path configured to electrically connect a plurality of first connections, wherein the plurality of first connections are first connecting points in first circuitry of a microchip, and wherein the electrical path comprises a conductive element;
a false electrical path configured to appear to connect a plurality of second connections but not electrically connecting the plurality of second connections, wherein the plurality of second connections are second connecting points in the first circuitry of the microchip; and
second circuitry configured to detect a disconnection of the electrical path, a connection of the false electrical path, or a combination thereof resulting from a reverse engineering process targeting the first circuitry, and to initiate an action to obstruct the reverse engineering process, wherein the second circuitry is in electrical communication with the electrical path and with the false electrical path, and wherein the second circuitry is embedded with the first circuitry.

2. The apparatus of claim 1 , wherein the conductive element comprises a metallic plate.

3. The apparatus of claim 1 , wherein the conductive element is positioned on a backside of the microchip.

4. The apparatus of claim 1 , wherein the plurality of first connections are selected automatically, randomly, or a combination thereof for inclusion within the electrical path.

5. The apparatus of claim 1 , wherein the plurality of second connections are selected automatically, randomly, or a combination thereof for inclusion within the false electrical path.

6. The apparatus of claim 1 , wherein the plurality of first connections and the plurality of second connections include through-silicon vias.

7. The apparatus of claim 1 , further comprising a signal transmitter configured to transmit a signal to the electrical path.

8. The apparatus of claim 1 , further comprising a signal receiver configured to receive a signal from the electrical path.

9. The apparatus of claim 1 , further comprising a bus configured to facilitate automatic selection, random selection, or a combination thereof of first connections for inclusion within the electrical path.

10. The apparatus of claim 1 , further comprising a bus configured to facilitate automatic selection, random selection, or a combination thereof of second connections for inclusion within the false electrical path.

11. The apparatus of claim 1 , further comprising program code executed by the second circuitry and configured to initiate the action for obstructing the reverse engineering process, and a computer readable storage device storing the program code.

12. The apparatus of claim 1 , wherein the action includes a shutdown operation, a spoofing operation, a self-destruct operation, or any combination thereof.

13. An apparatus comprising:
a false electrical path configured to appear to connect a plurality of connections but not electrically connecting the plurality of connections, wherein the plurality of connections are connecting points in first circuitry of a microchip; and
second circuitry configured to detect a connection of the false electrical path resulting from a reverse engineering process targeting the first circuitry and to initiate an action to obstruct the reverse engineering process, wherein the second circuitry is in electrical communication with the false electrical path, and wherein the second circuitry is embedded with the first circuitry.

14. A method of protecting security sensitive circuitry of a microchip from undesired analysis, the method comprising:
initializing the microchip;
selecting an electrical path from among a plurality of electrical paths, wherein the electrical path is configured to electrically connect a plurality of first connections, and wherein the plurality of first connections are connecting points in first circuitry of the microchip;
selecting a false electrical path from among a plurality of false electrical paths, wherein the false electrical path is configured to appear to connect a plurality of second connections but to not electrically connect the plurality of second connections, and wherein the plurality of second connections are second connecting points in the first circuitry of the microchip;
detecting, by second circuitry, a disconnection of the electrical path, a connection of the false electrical path, or a combination thereof resulting from a reverse engineering process targeting the first circuitry, wherein the second circuitry is in electrical communication with the electrical path and with the false electrical path; and
initiating an action to obstruct the reverse engineering process, wherein the second circuitry is embedded with the first circuitry.

15. The apparatus of claim 1 , wherein the second circuitry comprises:
a plurality of comparators;
a NAND gate; and
a defensive circuit,
wherein the plurality of comparators are configured to compare input signals from the plurality of first connections of the electrical path and the plurality of second connections of the false electrical path with reference signals and to output results to the NAND gate,
wherein the NAND gate is configured to output a signal to the defensive circuit in response to the results from the plurality of comparators, and
wherein the defensive circuit is configured to initiate the action to obstruct the reverse engineering process when the signal from the NAND gate indicates the disconnection of the electrical path, the connection of the false electrical path, or a combination thereof.

16. The apparatus of claim 13 , wherein the second circuitry comprises:
a plurality of comparators;
a NAND gate; and
a defensive circuit,
wherein the plurality of comparators are configured to compare input signals from the plurality of connections of the false electrical path with reference signals and to output results to the NAND gate,
wherein the NAND gate is configured to output a signal to the defensive circuit in response to the results from the plurality of comparators, and
wherein the defensive circuit is configured to initiate the action to obstruct the reverse engineering process when the signal from the NAND gate indicates the connection of the false electrical path.

17. The method of claim 14 , wherein the second circuitry comprises:
a plurality of comparators;
a NAND gate; and
a defensive circuit,
wherein the plurality of comparators are configured to compare input signals from the plurality of connections of the electrical path and the plurality of second connections of the false electrical path with reference signals and to output results to the NAND gate,
wherein the NAND gate is configured to output a signal to the defensive circuit in response to the results from the plurality of comparators, and
wherein the defensive circuit is configured to initiate the action to obstruct the reverse engineering process when the signal from the NAND gate indicates the disconnection of the electrical path, the connection of the false electrical path, or a combination thereof.

18. The apparatus of claim 13 , wherein the plurality of connections are selected automatically, randomly, or a combination thereof for inclusion within the false electrical path, and wherein the plurality of connections include through-silicon vias.

Assignees

• Bartley Gerald K
• Becker Darryl J
• Dahlen Paul E
• Germann Philip R
• Maki Andrew B
• Maxson Mark O
• Nilsen Carl-Otto
• IBM

Inventors

• Bartley Gerald K
• Becker Darryl J
• Dahlen Paul E
• Germann Philip R
• Maki Andrew B
• Maxson Mark O
• Nilsen Carl-Otto

Classifications

• G06F21/87 Primary

  by means of encapsulation, e.g. for integrated circuits · CPC title