Integrated physical coding sublayer and forward error correction in networking applications
US-2015381312-A1 · Dec 31, 2015 · US
US9003263B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9003263-B2 |
| Application number | US-201313742340-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 15, 2013 |
| Priority date | Jan 15, 2013 |
| Publication date | Apr 7, 2015 |
| Grant date | Apr 7, 2015 |
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A method of generating a hardware encoder includes generating a first directed graph characterizing a constraint set for a constrained system, identifying a scaling factor for an approximate eigenvector for the first directed graph, applying the scaling factor to the approximate eigenvector for the first directed graph to yield a scaled approximate eigenvector, partitioning arcs between each pair of states in the first directed graph, performing a state splitting operation on the first directed graph according to the partitioning of the arcs to yield a second directed graph, and generating the hardware encoder based on the second directed graph.
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What is claimed is: 1. A method of generating an encoder comprising: generating a first directed graph characterizing a constraint set for a constrained system; identifying a scaling factor for an approximate eigenvector for the first directed graph; applying the scaling factor to the approximate eigenvector for the first directed graph to yield a scaled approximate eigenvector; partitioning arcs between each pair of states in the first directed graph; performing a state s…
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