Method for memory storage and access
US-2024126640-A1 · Apr 18, 2024 · US
Memory system
US9003261B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9003261-B2 |
| Application number | US-201314017246-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 3, 2013 |
| Priority date | Nov 5, 2012 |
| Publication date | Apr 7, 2015 |
| Grant date | Apr 7, 2015 |
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Abstract
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A memory system includes a first nonvolatile memory, a second nonvolatile memory with a longer access latency than the first nonvolatile memory, a first error correction unit, a second error correction unit, and an interface. The first nonvolatile memory stores first data and a first error correction code generated for the first data. The second nonvolatile memory stores a second error correction code which is generated for the first data with a higher correction ability than that of the first error correction code. The first error correction unit performs error correction on the first data by using the first error correction code. The second error correction unit performs error correction on the first data by using the second error correction code. The interface transmits the first data after the error correction to a host.
First claim
Opening claim text (preview).
What is claimed is: 1. A memory system comprising: a first nonvolatile memory for storing first data and a first error correction code generated for the first data; a second nonvolatile memory which has a longer access latency than that of the first nonvolatile memory, for storing a second error correction code generated for the first data with a higher correction ability than that of the first error correction code; a first error correction unit configured to execute error co…
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- G06F11/1012Primary
Physics · mapped topic
- G06F11/1008Primary
Physics · mapped topic
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Frequently asked questions
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- What does patent US9003261B2 cover?
- A memory system includes a first nonvolatile memory, a second nonvolatile memory with a longer access latency than the first nonvolatile memory, a first error correction unit, a second error correction unit, and an interface. The first nonvolatile memory stores first data and a first error correction code generated for the first data. The second nonvolatile memory stores a second error correcti…
- Who is the assignee on this patent?
- Toshiba Kk
- What technology area does this patent fall under?
- Primary CPC classification G06F11/1012. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Apr 07 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).