Functional memory array testing with a transaction-level test engine

Patent metadata

Field	Value
Publication number	US-9003246-B2
Application number	US-201213631962-A
Country	US
Kind code	B2
Filing date	Sep 29, 2012
Priority date	Sep 29, 2012
Publication date	Apr 7, 2015
Grant date	Apr 7, 2015

Abstract

A memory subsystem includes a test engine coupled to a memory controller that can provide memory access transactions to the memory controller, bypassing a memory address decoder. The test engine hardware is configurable for different tests. The test engine identifies a range of addresses through which to iterate a test sequence in response to receiving a software instruction indicating a test to perform. For each iteration of the test, the test engine, via the selected hardware, generates a memory access transaction, selects an address from the range, and sends the transaction to the memory controller. The memory controller schedules memory device commands in response to the transaction, which causes the memory device to execute operations to carry out the transaction.

First claim

What is claimed is:

1. A method comprising:
receiving, by a test engine, a memory test software instruction indicating a test to perform on a memory device;
selecting hardware of the test engine to execute the test;
identifying a range of addresses through which to iterate a test sequence to execute the test; and
for each iteration of the test sequence to cover the range of addresses,
generating a memory access transaction;
determining a specific physical address in the a…

Assignees

• Intel Corp

Inventors

• Mozak Christopher P
• Schoenborn Theodore Z
• Shehadi James M

Classifications

• G11C2029/5602

  Physics · mapped topic

• G11C29/08 Primary

  Physics · mapped topic

• G11C29/56

  Physics · mapped topic