Cache system and processing apparatus

Patent metadata

Field	Value
Publication number	US-9003128-B2
Application number	US-201113234837-A
Country	US
Kind code	B2
Filing date	Sep 16, 2011
Priority date	Mar 24, 2011
Publication date	Apr 7, 2015
Grant date	Apr 7, 2015

Abstract

According to an embodiment, in a cache system, the sequence storage stores sequence data in association with each piece of data to be stored in the volatile cache memory in accordance with the number of pieces of data stored in the nonvolatile cache memory that have been unused for a longer period of time than the data stored in the volatile cache memory or the number of pieces of data stored in the nonvolatile cache memory that have been unused for a shorter period of time than the data stored in the volatile cache memory. The controller causes the first piece of data to be stored in the nonvolatile cache memory in a case where it can be determined that the first piece of data has been unused for a shorter period of time than any piece of the data stored in the nonvolatile cache memory.

First claim

What is claimed is:

1. A processor cache system, comprising:
a volatile cache memory included in a processor cache;
a nonvolatile cache memory included in the processor cache;
a sequence storage to store sequence data in association with each piece of data stored in the volatile cache memory, the sequence data representing the number of pieces of data stored in the nonvolatile cache memory and unused for a longer period of time than the piece of data stored in the volatile cache memory, or the number of pieces of data stored in the nonvolatile cache memory and unused for a shorter period of time than the piece of data stored in the volatile cache memory; and
a controller to cause a first piece of data stored in the volatile cache memory to be stored in the nonvolatile cache memory when the first piece of data is overwritten by a second piece of data having another address or when power of the volatile cache memory is turned off, in a case where it is determinable based on the stored sequence data associated with the first piece of data that the first piece of data has been unused for a shorter period of time than any pieces of the data stored in the nonvolatile cache memory, or when the power of the volatile cache memory is turned off;
wherein:
line numbers of the volatile cache memory are equal to line numbers of a first LRU memory,
line numbers of the nonvolatile cache memory are equal to line numbers of a second LRU memory,
when the first piece of data is written in the cache system, the first piece of data is written in the volatile cache memory,
when the second piece of data is stored in the volatile cache memory based on a read request, the second piece of data is read from the volatile cache memory, and
when the second piece of data is only stored in the nonvolatile cache memory based on the read request, the second piece of data is read from the nonvolatile cache memory.

2. The cache system according to claim 1 , wherein:
the second LRU memory stores, in association with each piece of the data stored in the nonvolatile cache memory, LRU data showing the order of lengths of the periods of time that the data has been unused, the order being among the data corresponding to a number of ways stored in the same line of the nonvolatile cache memory; and
the system further comprises an LRU update unit to update the LRU memory using the sequence data stored in the sequence storage in association with the first piece of data, when the controller causes the first piece of data to be stored in the nonvolatile cache memory.

3. The cache system according to claim 2 , further comprising an update processing unit to update, when any piece of the data in the nonvolatile cache memory is used, a sequence data stored in the sequence storage by using the LRU data stored in the second LRU memory in association with the piece of data in the nonvolatile cache memory.

4. The cache system according to claim wherein the controller causes the first piece of data to be stored not in the nonvolatile cache memory but in an upper storage device when the first piece of data stored in the volatile cache memory is overwritten by the second piece of data having another address or when power of the volatile cache memory is turned off, in a case where it is determinable based on the sequence data stored in the sequence storage in association with the first piece of data that the first piece of data has been unused for a longer period of time than all pieces of the data stored in the nonvolatile cache memory.

5. The cache system according to claim 1 , further comprising an already-copied storage to store copy information showing whether data identical to each piece of data in the volatile cache memory has been stored in the nonvolatile cache memory, in association with the piece of the data, wherein the controller causes the first piece of data to be stored in the nonvolatile cache memory when the first piece of data stored in the volatile cache memory is overwritten by second piece of data having another address or when power of the volatile cache memory is turned off, in a case where copy information has been stored which shows that data identical to the first piece of data has not been stored in the nonvolatile cache memory, in association with the first piece of data, when it is determinable based on the sequence data stored in the sequence storage in association with the first piece of data that the first piece of data has been unused for a shorter period of time than any pieces of the data stored in the nonvolatile cache memory.

6. The cache system according to claim 1 , wherein a number of lines of the volatile cache memory and a number of lines of the nonvolatile cache memory are equal to each other.

7. The cache system according to claim 1 , wherein the nonvolatile cache memory is a magnetoresistive memory.

8. A processing apparatus, comprising a processor cache system and a processor element, wherein the cache system comprises:
a volatile cache memory included in a processor cache;
a nonvolatile cache memory included in the processor cache;
a sequence storage to store sequence data in association with each piece of data stored in the volatile cache memory, the sequence data representing the number of pieces of data stored in the nonvolatile cache memory and unused for a longer period of time than the piece of data stored in the volatile cache memory, or the number of pieces of data stored in the nonvolatile cache memory and unused for a shorter period of time than the piece of data stored in the volatile cache memory; and
a controller to cause a first piece of data stored in the volatile cache memory to be stored in the nonvolatile cache memory when the first piece of data is overwritten by a second piece of data having another address or when power of the volatile cache memory is turned off, in a case where it is determinable based on the stored sequence data associated with the first piece of data that the first piece of data has been unused for a shorter period of time than any pieces of the data stored in the nonvolatile cache memory, or when the power of the volatile cache memory is turned off;
wherein:
line numbers of the volatile cache memory are equal to line numbers of a first LRU memory,
line numbers of the nonvolatile cache memory are equal to line numbers of a second LRU memory,
when the first piece of data is written in the cache system, the first data is written in the volatile cache memory,
when the second piece of data is stored in the volatile cache memory based on a read request, the second piece of data is read from the volatile cache memory, and
when the second piece of data is only stored in the nonvolatile cache memory based on the read request, the second piece of data is read from the nonvolatile cache memory; and
wherein the processor element performs an operation using data to be outputted from the cache system.

9. The processing apparatus according to claim 8 , wherein
the second LRU memory stores, in association with each piece of the data stored in the nonvolatile cache memory, LRU data showing the order of lengths of the periods of time that the data has been unused, the order being among the data corresponding to a number of ways stored in the same line of the nonvolatile cache memory; and
the processing apparatus further comprises an LRU update unit to update the LRU memory using the sequence data stored in the sequence storage in association with the first piece of data, when the controller causes the first piece of data to be stored in the nonvolatile cache memory.

10. The processing apparatus according to claim 9 , further comprising
an update processing unit to update, when any pie

Assignees

• Nomura Kumiko
• Abe Keiko
• Fujita Shinobu
• Toshiba Kk

Inventors

• Nomura Kumiko
• Abe Keiko
• Fujita Shinobu

Classifications

• G06F12/123

  with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list · CPC title

• Y02B60/1225

  Cross-Sectional Technologies · mapped topic

• G06F2212/225

  Hybrid cache memory, e.g. having both volatile and non-volatile portions · CPC title

• G06F12/0897 Primary

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title