Digital architecture for encoding a return-to-zero differential phase shift keying waveform

Patent metadata

Field	Value
Publication number	US-9001925-B1
Application number	US-201414317339-A
Country	US
Kind code	B1
Filing date	Jun 27, 2014
Priority date	Jun 27, 2014
Publication date	Apr 7, 2015
Grant date	Apr 7, 2015

Abstract

A return-to-zero control signal for controlling a modulator can be generated from two separate streams. A first data stream can include a pulse for each logical one that appears in an input data stream, while a second data stream can include a pulse for each logical zero that appears in the input data stream. The first and second data streams can be combined in a manner that yields the return-to-zero control signal. The first and second data streams can be generated in digital circuitry, such as an FPGA, to minimize the analog path for generating the return-to-zero control signal.

First claim

We claim:

1. A method for generating a return-to-zero control signal for controlling a modulator, the method comprising:
receiving an input data stream;
generating a first data stream from the input data stream, the first data stream including a pulse for each logical one that appears in the input data stream;
generating a second data stream from the input data stream, the second data stream including a pulse for each logical zero that appears in the input data stream;
combi…

Assignees

• L 3 Comm Corp

Inventors

• Christensen L Carl
• Uresk Bonnie A
• Perry Justin D
• Rivers Michael D
• Metz John L
• Steinhorst Larry H

Classifications

• H04B10/5561

  Electricity · mapped topic

• H04B10/5162 Primary

  Electricity · mapped topic