Active matrix substrate, display panel, and testing method for active matrix substrate and display panel

Patent metadata

Field	Value
Publication number	US-9000796-B2
Application number	US-201113295480-A
Country	US
Kind code	B2
Filing date	Nov 14, 2011
Priority date	Jan 6, 2010
Publication date	Apr 7, 2015
Grant date	Apr 7, 2015

Abstract

An active matrix substrate including: gate lines; source lines arranged in a direction orthogonal to each of the gate lines; a gate short-circuit line to short-circuit the gate lines; a source short-circuit line to short-circuit the source lines; gate line thin film transistors each having a drain electrode being connected to the corresponding one of the gate lines, and a source electrode being connected to the gate short-circuit line; and source line thin film transistors each having a drain electrode being connected to the corresponding one of the source lines, and a source electrode being connected to the source short-circuit line, in which the gate line thin film transistors and the source line thin film transistors are of depletion-mode, and the gate electrode of each of the source line thin film transistors is connected to the gate short-circuit line.

First claim

What is claimed is:

1. An active matrix substrate, comprising:
a substrate;
a plurality of gate lines arranged on the substrate:
a plurality of source lines arranged on the substrate, in a direction orthogonal to each of the plurality of gate lines;
a gate short-circuit line arranged on a peripheral region of the substrate to short-circuit the plurality of gate lines;
a source short-circuit line arranged on a peripheral region of the substrate to short-circuit the plurality of source lines;
a plurality of gate line thin film transistors each provided for a corresponding one of the plurality of gate lines and each having a source electrode, a drain electrode, and a gate electrode, one of the source electrode and the drain electrode being connected to the corresponding one of the plurality of gate lines, and an other of the source electrode and the drain electrode being connected to the gate short-circuit line; and
a plurality of source line thin film transistors each provided for a corresponding one of the plurality of source lines and each having a source electrode, a drain electrode, and a gate electrode, one of the source electrode and the drain electrode being connected to the corresponding one of the plurality of source lines, and an other of the source electrode and the drain electrode being connected to the source short-circuit line,
wherein the plurality of gate line thin film transistors and the plurality of source line thin film transistors are of depletion-mode,
the gate electrode of each of the plurality of source line thin film transistors is connected to the gate short-circuit line,
a load thin film transistor having a source electrode and a gate electrode which are short-circuited is inserted between the gate electrode of each of the plurality of source line thin film transistors and the gate short-circuit line, the load thin film transistor being for setting an electric potential of the gate short-circuit line to an electric potential of the gate electrode of each of the plurality of source line thin film transistors, and
the gate electrode of each of the plurality of gate line thin film transistor is connected to the gate electrode of each of the plurality of source line thin film transistors.

2. An active matrix substrate, comprising:
a substrate;
a plurality of gate lines arranged on the substrate;
a plurality of source lines arranged on the substrate, in a direction orthogonal to each of the plurality of gate lines;
a gate short-circuit line arranged on a peripheral region of the substrate to short-circuit the plurality of gate lines;
a source short-circuit line arranged on a peripheral region of the substrate to short-circuit the plurality of source lines;
a plurality of gate line thin film transistors each provided for a corresponding one of the plurality of gate lines and each having a source electrode and a drain electrode, one of the source electrode and the drain electrode being connected to the corresponding one of the plurality of gate lines, and an other of the source electrode and the drain electrode being connected to the gate short-circuit line;
a plurality of source line thin film transistors each provided for a corresponding one of the plurality of source lines and each having a source electrode, a drain electrode, and a gate electrode, one of the source electrode and the drain electrode being connected to the corresponding one of the plurality of source lines, and an other of the source electrode and the drain electrode being connected to the source short-circuit line; and
a separating thin film transistor capable of separating an electric potential of the gate short-circuit line from an electric potential of the source short-circuit line, the separating thin film transistor having a source electrode, a drain electrode, and a gate electrode, one of the source electrode and the drain electrode being connected to the gate short-circuit line, an other of the source electrode and the drain electrode being connected to the source short-circuit line, and the gate electrode being connected to the gate electrode of each of the plurality of source line thin film transistors,
wherein the plurality of gate line thin film transistors and the plurality of source line thin film transistors are of depletion-mode, and
the gate electrode of each of the plurality of source line thin film transistors is connected to the gate short-circuit line.

3. The active matrix substrate according to claim 2 ,
wherein the electric potential of the gate short-circuit line is set to a same electric potential as the electric potential of the source short-circuit line when no scanning signal voltage is supplied to the plurality of gate lines, and
the electric potential of the gate short-circuit line is set to an electric potential separate from the electric potential of the source short-circuit line when a scanning signal voltage is supplied to the plurality of gate lines.

4. A testing method of a display panel, that includes an active matrix display and light-emitting pixels,
the active matrix substrate, comprising:
a substrate;
a plurality of gate lines arranged on the substrate:
a plurality of source lines arranged on the substrate, in a direction orthogonal to each of the plurality of gate lines;
a gate short-circuit line arranged on a peripheral region of the substrate to short-circuit the plurality of gate lines;
a source short-circuit line arranged on a peripheral region of the substrate to short-circuit the plurality of source lines;
a plurality of gate line thin film transistors each provided for a corresponding one of the plurality of gate lines and each having a source electrode and a drain electrode, one of the source electrode and the drain electrode being connected to the corresponding one of the plurality of gate lines, and an other of the source electrode and the drain electrode being connected to the gate short-circuit line; and
a plurality of source line thin film transistors each provided for a corresponding one of the plurality of source lines and each having a source electrode a drain electrode and a gate electrode, one of the source electrode and the drain electrode being connected to the corresponding one of the plurality of source lines, and an other of the source electrode and the drain electrode being connected to the source short-circuit line,

the plurality of gate line thin film transistors and the plurality of source line thin film transistors being of depletion-mode,
the gate electrode of each of the plurality of source line thin film transistors being connected to the gate short-circuit line,
the light-emitting pixels being arranged at intersections of the plurality of gate lines and the plurality of source lines in the active matrix substrate, and
the testing method comprising:
attempting to operate a circuit of the light-emitting pixels by applying a negative voltage to the gate electrode of each of the plurality of source line thin film transistors from the gate short-circuit line to set the plurality of source line thin film transistors to a non-conducting state; and
testing a circuit element of each of the light-emitting pixels based on a result of the circuit operation attempted in the attempting.

5. The testing method of the display panel according to claim 4 ,
wherein circuit elements of the light-emitting pixels connected to the plurality of source lines and the plurality of gate lines are protected from static electricity by conducting the plurality of source line thin film transistors and the plurality of gate line thin film transistors by applying zero or positive voltage to the gate electrode of each of the plurality of source line thin film transistors and a gate electrode of each of the plurality of gate line thin film transistors.

Assignees

• Shirouzu Hiroshi
• Panasonic Corp

Inventors

• Shirouzu Hiroshi

Classifications

• H10D89/931

  characterised by the dispositions of the protective arrangements · CPC title

• G02F2203/69

  Arrangements or methods for testing or calibrating a device · CPC title

• H01L27/0296

  Electricity · mapped topic

• G09G2330/04

  Display protection · CPC title

• G02F1/1309

  Repairing; Testing · CPC title