Power detector circuit using native transistor
US-9780776-B1 · Oct 3, 2017 · US
Voltage detecting circuit
US9000751B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9000751-B2 |
| Application number | US-201213396235-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 14, 2012 |
| Priority date | Feb 18, 2011 |
| Publication date | Apr 7, 2015 |
| Grant date | Apr 7, 2015 |
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Abstract
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In a voltage detecting circuit, a transistor is configured as a P-type MOSFET, and includes a source connected with an input terminal, a gate connected with a ground voltage terminal and a drain connected with an output terminal. A transistor is configured as a P-type MOSFET, and includes a gate and a source connected with the output terminal and a drain connected with the ground terminal. Gate width and gate length of the transistor and gate width and gate length of the transistor are adjusted so that source-drain current flowing between the source and the drain of the transistor becomes equal to source-drain current flowing between the source and the drain of the transistor when the voltage applied to the input terminal is set to be preset trigger voltage. This configuration accomplishes detecting that the input voltage exceeds the trigger voltage with simple configuration.
First claim
Opening claim text (preview).
What is claimed is: 1. A voltage detecting circuit configured to detect that voltage applied to an input terminal exceeds preset trigger voltage, the voltage detecting circuit comprising: a first transistor configured as a P-type field-effect transistor, and including a source connected with the input terminal, a gate connected with a ground voltage terminal and a drain connected with an output terminal; and a second transistor configured as a P-type field-effect transistor incl…
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- G01R19/16519Primary
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9000751B2 cover?
- In a voltage detecting circuit, a transistor is configured as a P-type MOSFET, and includes a source connected with an input terminal, a gate connected with a ground voltage terminal and a drain connected with an output terminal. A transistor is configured as a P-type MOSFET, and includes a gate and a source connected with the output terminal and a drain connected with the ground terminal. Gate…
- Who is the assignee on this patent?
- Chen Po-Hung, Takamiya Makoto, Sakurai Takayasu, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification G01R19/16519. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Apr 07 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).